stm32_rust_template::mcu::stm32f407

Enum IRQn

#[repr(u8)]pub enum IRQn {
Show 81 variants    WWDG = 0,
    PVD = 1,
    TAMP_STAMP = 2,
    RTC_WKUP = 3,
    RCC = 5,
    EXTI0 = 6,
    EXTI1 = 7,
    EXTI2 = 8,
    EXTI3 = 9,
    EXTI4 = 10,
    DMA1_Stream0 = 11,
    DMA1_Stream1 = 12,
    DMA1_Stream2 = 13,
    DMA1_Stream3 = 14,
    DMA1_Stream4 = 15,
    DMA1_Stream5 = 16,
    DMA1_Stream6 = 17,
    ADC = 18,
    CAN1_TX = 19,
    CAN1_RX0 = 20,
    CAN1_RX1 = 21,
    CAN1_SCE = 22,
    EXTI9_5 = 23,
    TIM1_BRK_TIM9 = 24,
    TIM1_UP_TIM10 = 25,
    TIM1_TRG_COM_TIM11 = 26,
    TIM1_CC = 27,
    TIM2 = 28,
    TIM3 = 29,
    TIM4 = 30,
    I2C1_EV = 31,
    I2C1_ER = 32,
    I2C2_EV = 33,
    I2C2_ER = 34,
    SPI1 = 35,
    SPI2 = 36,
    USART1 = 37,
    USART2 = 38,
    USART3 = 39,
    EXTI15_10 = 40,
    RTC_Alarm = 41,
    OTG_FS_WKUP = 42,
    TIM8_BRK_TIM12 = 43,
    TIM8_UP_TIM13 = 44,
    TIM8_TRG_COM_TIM14 = 45,
    TIM8_CC = 46,
    DMA1_Stream7 = 47,
    FSMC = 48,
    SDIO = 49,
    TIM5 = 50,
    SPI3 = 51,
    UART4 = 52,
    UART5 = 53,
    TIM6_DAC = 54,
    TIM7 = 55,
    DMA2_Stream0 = 56,
    DMA2_Stream1 = 57,
    DMA2_Stream2 = 58,
    DMA2_Stream3 = 59,
    DMA2_Stream4 = 60,
    ETH = 61,
    ETH_WKUP = 62,
    CAN2_TX = 63,
    CAN2_RX0 = 64,
    CAN2_RX1 = 65,
    CAN2_SCE = 66,
    OTG_FS = 67,
    DMA2_Stream5 = 68,
    DMA2_Stream6 = 69,
    DMA2_Stream7 = 70,
    USART6 = 71,
    I2C3_EV = 72,
    I2C3_ER = 73,
    OTG_HS_EP1_OUT = 74,
    OTG_HS_EP1_IN = 75,
    OTG_HS_WKUP = 76,
    OTG_HS = 77,
    DCMI = 78,
    CRYP = 79,
    HASH_RNG = 80,
    FPU = 81,
}

Variants§

WWDG = 0

PVD = 1

TAMP_STAMP = 2

RTC_WKUP = 3

RCC = 5

EXTI0 = 6

EXTI1 = 7

EXTI2 = 8

EXTI3 = 9

EXTI4 = 10

DMA1_Stream0 = 11

DMA1_Stream1 = 12

DMA1_Stream2 = 13

DMA1_Stream3 = 14

DMA1_Stream4 = 15

DMA1_Stream5 = 16

DMA1_Stream6 = 17

ADC = 18

CAN1_TX = 19

CAN1_RX0 = 20

CAN1_RX1 = 21

CAN1_SCE = 22

EXTI9_5 = 23

TIM1_BRK_TIM9 = 24

TIM1_UP_TIM10 = 25

TIM1_TRG_COM_TIM11 = 26

TIM1_CC = 27

TIM2 = 28

TIM3 = 29

TIM4 = 30

I2C1_EV = 31

I2C1_ER = 32

I2C2_EV = 33

I2C2_ER = 34

SPI1 = 35

SPI2 = 36

USART1 = 37

USART2 = 38

USART3 = 39

EXTI15_10 = 40

RTC_Alarm = 41

OTG_FS_WKUP = 42

TIM8_BRK_TIM12 = 43

TIM8_UP_TIM13 = 44

TIM8_TRG_COM_TIM14 = 45

TIM8_CC = 46

DMA1_Stream7 = 47

FSMC = 48

SDIO = 49

TIM5 = 50

SPI3 = 51

UART4 = 52

UART5 = 53

TIM6_DAC = 54

TIM7 = 55

DMA2_Stream0 = 56

DMA2_Stream1 = 57

DMA2_Stream2 = 58

DMA2_Stream3 = 59

DMA2_Stream4 = 60

ETH = 61

ETH_WKUP = 62

CAN2_TX = 63

CAN2_RX0 = 64

CAN2_RX1 = 65

CAN2_SCE = 66

OTG_FS = 67

DMA2_Stream5 = 68

DMA2_Stream6 = 69

DMA2_Stream7 = 70

USART6 = 71

I2C3_EV = 72

I2C3_ER = 73

OTG_HS_EP1_OUT = 74

OTG_HS_EP1_IN = 75

OTG_HS_WKUP = 76

OTG_HS = 77

DCMI = 78

CRYP = 79

HASH_RNG = 80

FPU = 81

Auto Trait Implementations§

impl Freeze for IRQn

impl RefUnwindSafe for IRQn

impl Send for IRQn

impl Sync for IRQn

impl Unpin for IRQn

impl UnwindSafe for IRQn

Blanket Implementations§

impl<T> Any for T
where T: 'static + ?Sized,

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fn borrow_mut(&mut self) -> &mut T

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impl<T> From<T> for T

fn from(t: T) -> T

Returns the argument unchanged.

impl<T, U> Into<U> for T
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type Error = Infallible

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fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>

Performs the conversion.

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type Error = <U as TryFrom<T>>::Error

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fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>

Performs the conversion.