stm32_rust_template/mcu/stm32f407/
mod.rs

1//! # STM32F407 MCU Implementation
2//!
3//! Contains register definitions, memory maps, and peripheral configurations
4//! specific to the STM32F407 microcontroller family.
5//!
6//! This module provides base addresses for all peripherals, interrupt numbers,
7//! and type-safe register access through the PeripheralAccess trait.
8pub const TIM2_BASEADDR: u32 = 0x40000000;
9pub const TIM3_BASEADDR: u32 = 0x40000400;
10pub const TIM4_BASEADDR: u32 = 0x40000800;
11pub const TIM5_BASEADDR: u32 = 0x40000C00;
12pub const TIM6_BASEADDR: u32 = 0x40001000;
13pub const TIM7_BASEADDR: u32 = 0x40001400;
14pub const TIM12_BASEADDR: u32 = 0x40001800;
15pub const TIM13_BASEADDR: u32 = 0x40001C00;
16pub const TIM14_BASEADDR: u32 = 0x40002000;
17pub const RTC_BASEADDR: u32 = 0x40002800;
18pub const WWDG_BASEADDR: u32 = 0x40002C00;
19pub const IWDG_BASEADDR: u32 = 0x40003000;
20pub const I2S2EXT_BASEADDR: u32 = 0x40003400;
21pub const SPI2_BASEADDR: u32 = 0x40003800;
22pub const SPI3_BASEADDR: u32 = 0x40003C00;
23pub const I2S3EXT_BASEADDR: u32 = 0x40004000;
24pub const USART2_BASEADDR: u32 = 0x40004400;
25pub const USART3_BASEADDR: u32 = 0x40004800;
26pub const UART4_BASEADDR: u32 = 0x40004C00;
27pub const UART5_BASEADDR: u32 = 0x40005000;
28pub const I2C1_BASEADDR: u32 = 0x40005400;
29pub const I2C2_BASEADDR: u32 = 0x40005800;
30pub const I2C3_BASEADDR: u32 = 0x40005C00;
31pub const CAN1_BASEADDR: u32 = 0x40006400;
32pub const CAN2_BASEADDR: u32 = 0x40006800;
33pub const PWR_BASEADDR: u32 = 0x40007000;
34pub const DAC_BASEADDR: u32 = 0x40007400;
35pub const UART7_BASEADDR: u32 = 0x40007800;
36pub const UART8_BASEADDR: u32 = 0x40007C00;
37pub const TIM1_BASEADDR: u32 = 0x40010000;
38pub const TIM8_BASEADDR: u32 = 0x40010400;
39pub const USART1_BASEADDR: u32 = 0x40011000;
40pub const USART6_BASEADDR: u32 = 0x40011400;
41pub const ADC1_BASEADDR: u32 = 0x40012000;
42pub const ADC2_BASEADDR: u32 = 0x40012100;
43pub const ADC3_BASEADDR: u32 = 0x40012200;
44pub const ADC_COMMON_BASEADDR: u32 = 0x40012300;
45pub const SDIO_BASEADDR: u32 = 0x40012C00;
46pub const SPI1_BASEADDR: u32 = 0x40013000;
47pub const SPI4_BASEADDR: u32 = 0x40013400;
48pub const SYSCFG_BASEADDR: u32 = 0x40013800;
49pub const EXTI_BASEADDR: u32 = 0x40013C00;
50pub const TIM9_BASEADDR: u32 = 0x40014000;
51pub const TIM10_BASEADDR: u32 = 0x40014400;
52pub const TIM11_BASEADDR: u32 = 0x40014800;
53pub const SPI5_BASEADDR: u32 = 0x40015000;
54pub const SPI6_BASEADDR: u32 = 0x40015400;
55pub const SAI1_BASEADDR: u32 = 0x40015800;
56pub const GPIOA_BASEADDR: u32 = 0x40020000;
57pub const GPIOB_BASEADDR: u32 = 0x40020400;
58pub const GPIOC_BASEADDR: u32 = 0x40020800;
59pub const GPIOD_BASEADDR: u32 = 0x40020C00;
60pub const GPIOE_BASEADDR: u32 = 0x40021000;
61pub const GPIOF_BASEADDR: u32 = 0x40021400;
62pub const GPIOG_BASEADDR: u32 = 0x40021800;
63pub const GPIOH_BASEADDR: u32 = 0x40021C00;
64pub const GPIOI_BASEADDR: u32 = 0x40022000;
65pub const GPIOJ_BASEADDR: u32 = 0x40022400;
66pub const GPIOK_BASEADDR: u32 = 0x40022800;
67pub const CRC_BASEADDR: u32 = 0x40023000;
68pub const RCC_BASEADDR: u32 = 0x40023800;
69pub const FLASH_R_BASEADDR: u32 = 0x40023C00;
70pub const DMA1_BASEADDR: u32 = 0x40026000;
71pub const DMA2_BASEADDR: u32 = 0x40026400;
72pub const ETH_MAC_BASEADDR: u32 = 0x40028000;
73pub const ETH_MMC_BASEADDR: u32 = 0x40028100;
74pub const ETH_PTP_BASEADDR: u32 = 0x40028700;
75pub const ETH_DMA_BASEADDR: u32 = 0x40029000;
76pub const DMA2D_BASEADDR: u32 = 0x4002B000;
77pub const RNG_BASEADDR: u32 = 0x50060800;
78pub const FSMC_BASEADDR: u32 = 0xA0000000;
79pub const DBGMCU_BASEADDR: u32 = 0xE0042000;
80pub const USB_OTG_HS_BASEADDR: u32 = 0x40040000;
81pub const USB_OTG_FS_BASEADDR: u32 = 0x50000000;
82pub const DCMI_BASEADDR: u32 = 0x50050000;
83pub const CRYP_BASEADDR: u32 = 0x50060000;
84pub const HASH_BASEADDR: u32 = 0x50060400;
85pub const LTDC_BASEADDR: u32 = 0x40016800;
86pub const FMC_BASEADDR: u32 = 0xA0000000;
87
88/*
89 * IRQ(Interrupt Request) Numbers of STM32F407x MCU
90 */
91#[allow(non_camel_case_types)]
92#[repr(u8)]
93pub enum IRQn {
94    WWDG = 0,
95    PVD = 1,
96    TAMP_STAMP = 2,
97    RTC_WKUP = 3,
98    // Reserved = 4,
99    RCC = 5,
100    EXTI0 = 6,
101    EXTI1 = 7,
102    EXTI2 = 8,
103    EXTI3 = 9,
104    EXTI4 = 10,
105    DMA1_Stream0 = 11,
106    DMA1_Stream1 = 12,
107    DMA1_Stream2 = 13,
108    DMA1_Stream3 = 14,
109    DMA1_Stream4 = 15,
110    DMA1_Stream5 = 16,
111    DMA1_Stream6 = 17,
112    ADC = 18,
113    CAN1_TX = 19,
114    CAN1_RX0 = 20,
115    CAN1_RX1 = 21,
116    CAN1_SCE = 22,
117    EXTI9_5 = 23,
118    TIM1_BRK_TIM9 = 24,
119    TIM1_UP_TIM10 = 25,
120    TIM1_TRG_COM_TIM11 = 26,
121    TIM1_CC = 27,
122    TIM2 = 28,
123    TIM3 = 29,
124    TIM4 = 30,
125    I2C1_EV = 31,
126    I2C1_ER = 32,
127    I2C2_EV = 33,
128    I2C2_ER = 34,
129    SPI1 = 35,
130    SPI2 = 36,
131    USART1 = 37,
132    USART2 = 38,
133    USART3 = 39,
134    EXTI15_10 = 40,
135    RTC_Alarm = 41,
136    OTG_FS_WKUP = 42,
137    TIM8_BRK_TIM12 = 43,
138    TIM8_UP_TIM13 = 44,
139    TIM8_TRG_COM_TIM14 = 45,
140    TIM8_CC = 46,
141    DMA1_Stream7 = 47,
142    FSMC = 48,
143    SDIO = 49,
144    TIM5 = 50,
145    SPI3 = 51,
146    UART4 = 52,
147    UART5 = 53,
148    TIM6_DAC = 54,
149    TIM7 = 55,
150    DMA2_Stream0 = 56,
151    DMA2_Stream1 = 57,
152    DMA2_Stream2 = 58,
153    DMA2_Stream3 = 59,
154    DMA2_Stream4 = 60,
155    ETH = 61,
156    ETH_WKUP = 62,
157    CAN2_TX = 63,
158    CAN2_RX0 = 64,
159    CAN2_RX1 = 65,
160    CAN2_SCE = 66,
161    OTG_FS = 67,
162    DMA2_Stream5 = 68,
163    DMA2_Stream6 = 69,
164    DMA2_Stream7 = 70,
165    USART6 = 71,
166    I2C3_EV = 72,
167    I2C3_ER = 73,
168    OTG_HS_EP1_OUT = 74,
169    OTG_HS_EP1_IN = 75,
170    OTG_HS_WKUP = 76,
171    OTG_HS = 77,
172    DCMI = 78,
173    CRYP = 79,
174    HASH_RNG = 80,
175    FPU = 81,
176}
177
178pub trait PeripheralAccess {
179    const BASE_ADDRESS: u32;
180    type RegisterBlock;
181
182    fn ptr() -> *const Self::RegisterBlock {
183        Self::BASE_ADDRESS as *const Self::RegisterBlock
184    }
185
186    fn ptr_mut() -> *mut Self::RegisterBlock {
187        Self::BASE_ADDRESS as *mut Self::RegisterBlock
188    }
189}
190
191pub mod adc;
192pub mod gpio;
193pub mod i2c;
194pub mod rcc;
195pub mod spi;
196pub mod timer;
197pub mod usart;
stm32_rust_template/mcu/stm32f407/mod.rs

stm32_rust_template/mcu/stm32f407/
mod.rs
