Structs§
Enums§
Constants§
- ARR_
ARR_ MASK - ARR_
ARR_ POS - ARR_
ARR_ WIDTH - CCER_
CC1E_ MASK - CCER_
CC1E_ POS - CCER_
CC1E_ WIDTH - CCER_
CC1NP_ MASK - CCER_
CC1NP_ POS - CCER_
CC1NP_ WIDTH - CCER_
CC1P_ MASK - CCER_
CC1P_ POS - CCER_
CC1P_ WIDTH - CCER_
CC2E_ MASK - CCER_
CC2E_ POS - CCER_
CC2E_ WIDTH - CCER_
CC2NP_ MASK - CCER_
CC2NP_ POS - CCER_
CC2NP_ WIDTH - CCER_
CC2P_ MASK - CCER_
CC2P_ POS - CCER_
CC2P_ WIDTH - CCER_
CC3E_ MASK - CCER_
CC3E_ POS - CCER_
CC3E_ WIDTH - CCER_
CC3NP_ MASK - CCER_
CC3NP_ POS - CCER_
CC3NP_ WIDTH - CCER_
CC3P_ MASK - CCER_
CC3P_ POS - CCER_
CC3P_ WIDTH - CCER_
CC4E_ MASK - CCER_
CC4E_ POS - CCER_
CC4E_ WIDTH - CCER_
CC4NP_ MASK - CCER_
CC4NP_ POS - CCER_
CC4NP_ WIDTH - CCER_
CC4P_ MASK - CCER_
CC4P_ POS - CCER_
CC4P_ WIDTH - CCMR1_
CC1S_ MASK - CCMR1_
CC1S_ OUTPUT - CCMR1_
CC1S_ POS - CCMR1_
CC1S_ TI1 - CCMR1_
CC1S_ TI2 - CCMR1_
CC1S_ TRC - CCMR1_
CC1S_ WIDTH - CCMR1_
CC2S_ MASK - CCMR1_
CC2S_ OUTPUT - CCMR1_
CC2S_ POS - CCMR1_
CC2S_ TI1 - CCMR1_
CC2S_ TI2 - CCMR1_
CC2S_ TRC - CCMR1_
CC2S_ WIDTH - CCMR1_
IC1F_ FCK_ INT_ N2 - CCMR1_
IC1F_ FCK_ INT_ N4 - CCMR1_
IC1F_ FCK_ INT_ N8 - CCMR1_
IC1F_ FDTS_ DIV2_ N6 - CCMR1_
IC1F_ FDTS_ DIV2_ N8 - CCMR1_
IC1F_ FDTS_ DIV4_ N6 - CCMR1_
IC1F_ FDTS_ DIV4_ N8 - CCMR1_
IC1F_ FDTS_ DIV8_ N6 - CCMR1_
IC1F_ FDTS_ DIV8_ N8 - CCMR1_
IC1F_ FDTS_ DIV16_ N5 - CCMR1_
IC1F_ FDTS_ DIV16_ N6 - CCMR1_
IC1F_ FDTS_ DIV16_ N8 - CCMR1_
IC1F_ FDTS_ DIV32_ N5 - CCMR1_
IC1F_ FDTS_ DIV32_ N6 - CCMR1_
IC1F_ FDTS_ DIV32_ N8 - CCMR1_
IC1F_ MASK - CCMR1_
IC1F_ NOFILTER - CCMR1_
IC1F_ POS - CCMR1_
IC1F_ WIDTH - CCMR1_
IC1PSC_ MASK - CCMR1_
IC1PSC_ POS - CCMR1_
IC1PSC_ WIDTH - CCMR1_
IC2F_ MASK - CCMR1_
IC2F_ POS - CCMR1_
IC2F_ WIDTH - CCMR1_
IC2PSC_ MASK - CCMR1_
IC2PSC_ POS - CCMR1_
IC2PSC_ WIDTH - CCMR1_
OC1CE_ MASK - CCMR1_
OC1CE_ POS - CCMR1_
OC1CE_ WIDTH - CCMR1_
OC1FE_ MASK - CCMR1_
OC1FE_ POS - CCMR1_
OC1FE_ WIDTH - CCMR1_
OC1M_ ACTIVEONMATCH - CCMR1_
OC1M_ FORCEACTIVE - CCMR1_
OC1M_ FORCEINACTIVE - CCMR1_
OC1M_ FROZEN - CCMR1_
OC1M_ INACTIVEONMATCH - CCMR1_
OC1M_ MASK - CCMR1_
OC1M_ POS - CCMR1_
OC1M_ PWMMOD E1 - CCMR1_
OC1M_ PWMMOD E2 - CCMR1_
OC1M_ TOGGLE - CCMR1_
OC1M_ WIDTH - CCMR1_
OC1PE_ DISABLED - CCMR1_
OC1PE_ ENABLED - CCMR1_
OC1PE_ MASK - CCMR1_
OC1PE_ POS - CCMR1_
OC1PE_ WIDTH - CCMR1_
OC2CE_ MASK - CCMR1_
OC2CE_ POS - CCMR1_
OC2CE_ WIDTH - CCMR1_
OC2FE_ MASK - CCMR1_
OC2FE_ POS - CCMR1_
OC2FE_ WIDTH - CCMR1_
OC2M_ MASK - CCMR1_
OC2M_ POS - CCMR1_
OC2M_ WIDTH - CCMR1_
OC2PE_ DISABLED - CCMR1_
OC2PE_ ENABLED - CCMR1_
OC2PE_ MASK - CCMR1_
OC2PE_ POS - CCMR1_
OC2PE_ WIDTH - CCMR2_
CC3S_ MASK - CCMR2_
CC3S_ OUTPUT - CCMR2_
CC3S_ POS - CCMR2_
CC3S_ TI3 - CCMR2_
CC3S_ TI4 - CCMR2_
CC3S_ TRC - CCMR2_
CC3S_ WIDTH - CCMR2_
CC4S_ MASK - CCMR2_
CC4S_ OUTPUT - CCMR2_
CC4S_ POS - CCMR2_
CC4S_ TI3 - CCMR2_
CC4S_ TI4 - CCMR2_
CC4S_ TRC - CCMR2_
CC4S_ WIDTH - CCMR2_
IC3F_ MASK - CCMR2_
IC3F_ POS - CCMR2_
IC3F_ WIDTH - CCMR2_
IC3PSC_ MASK - CCMR2_
IC3PSC_ POS - CCMR2_
IC3PSC_ WIDTH - CCMR2_
IC4F_ MASK - CCMR2_
IC4F_ POS - CCMR2_
IC4F_ WIDTH - CCMR2_
IC4PSC_ MASK - CCMR2_
IC4PSC_ POS - CCMR2_
IC4PSC_ WIDTH - CCMR2_
OC3CE_ MASK - CCMR2_
OC3CE_ POS - CCMR2_
OC3CE_ WIDTH - CCMR2_
OC3FE_ MASK - CCMR2_
OC3FE_ POS - CCMR2_
OC3FE_ WIDTH - CCMR2_
OC3M_ ACTIVEONMATCH - CCMR2_
OC3M_ FORCEACTIVE - CCMR2_
OC3M_ FORCEINACTIVE - CCMR2_
OC3M_ FROZEN - CCMR2_
OC3M_ INACTIVEONMATCH - CCMR2_
OC3M_ MASK - CCMR2_
OC3M_ POS - CCMR2_
OC3M_ PWMMOD E1 - CCMR2_
OC3M_ PWMMOD E2 - CCMR2_
OC3M_ TOGGLE - CCMR2_
OC3M_ WIDTH - CCMR2_
OC3PE_ DISABLED - CCMR2_
OC3PE_ ENABLED - CCMR2_
OC3PE_ MASK - CCMR2_
OC3PE_ POS - CCMR2_
OC3PE_ WIDTH - CCMR2_
OC4CE_ MASK - CCMR2_
OC4CE_ POS - CCMR2_
OC4CE_ WIDTH - CCMR2_
OC4FE_ MASK - CCMR2_
OC4FE_ POS - CCMR2_
OC4FE_ WIDTH - CCMR2_
OC4M_ MASK - CCMR2_
OC4M_ POS - CCMR2_
OC4M_ WIDTH - CCMR2_
OC4PE_ DISABLED - CCMR2_
OC4PE_ ENABLED - CCMR2_
OC4PE_ MASK - CCMR2_
OC4PE_ POS - CCMR2_
OC4PE_ WIDTH - CCR1_
CCR_ MASK - CCR1_
CCR_ POS - CCR1_
CCR_ WIDTH - CCR2_
CCR_ MASK - CCR2_
CCR_ POS - CCR2_
CCR_ WIDTH - CCR3_
CCR_ MASK - CCR3_
CCR_ POS - CCR3_
CCR_ WIDTH - CCR4_
CCR_ MASK - CCR4_
CCR_ POS - CCR4_
CCR_ WIDTH - CNT_
CNT_ MASK - CNT_
CNT_ POS - CNT_
CNT_ WIDTH - CR1_
ARPE_ DISABLED - CR1_
ARPE_ ENABLED - CR1_
ARPE_ MASK - CR1_
ARPE_ POS - CR1_
ARPE_ WIDTH - CR1_
CEN_ DISABLED - CR1_
CEN_ ENABLED - CR1_
CEN_ MASK - CR1_
CEN_ POS - CR1_
CEN_ WIDTH - CR1_
CKD_ DIV1 - CR1_
CKD_ DIV2 - CR1_
CKD_ DIV4 - CR1_
CKD_ MASK - CR1_
CKD_ POS - CR1_
CKD_ WIDTH - CR1_
CMS_ CENTERALIGNE D1 - CR1_
CMS_ CENTERALIGNE D2 - CR1_
CMS_ CENTERALIGNE D3 - CR1_
CMS_ EDGEALIGNED - CR1_
CMS_ MASK - CR1_
CMS_ POS - CR1_
CMS_ WIDTH - CR1_
DIR_ DOWN - CR1_
DIR_ MASK - CR1_
DIR_ POS - CR1_
DIR_ UP - CR1_
DIR_ WIDTH - CR1_
OPM_ DISABLED - CR1_
OPM_ ENABLED - CR1_
OPM_ MASK - CR1_
OPM_ POS - CR1_
OPM_ WIDTH - CR1_
UDIS_ DISABLED - CR1_
UDIS_ ENABLED - CR1_
UDIS_ MASK - CR1_
UDIS_ POS - CR1_
UDIS_ WIDTH - CR1_
URS_ ANYEVENT - CR1_
URS_ COUNTERONLY - CR1_
URS_ MASK - CR1_
URS_ POS - CR1_
URS_ WIDTH - CR2_
CCDS_ MASK - CR2_
CCDS_ ONCOMPARE - CR2_
CCDS_ ONUPDATE - CR2_
CCDS_ POS - CR2_
CCDS_ WIDTH - CR2_
MMS_ COMPAREO C1 - CR2_
MMS_ COMPAREO C2 - CR2_
MMS_ COMPAREO C3 - CR2_
MMS_ COMPAREO C4 - CR2_
MMS_ COMPAREPULSE - CR2_
MMS_ ENABLE - CR2_
MMS_ MASK - CR2_
MMS_ POS - CR2_
MMS_ RESET - CR2_
MMS_ UPDATE - CR2_
MMS_ WIDTH - CR2_
TI1S_ MASK - CR2_
TI1S_ NORMAL - CR2_
TI1S_ POS - CR2_
TI1S_ WIDTH - CR2_
TI1S_ XOR - DCR_
DBA_ MASK - DCR_
DBA_ POS - DCR_
DBA_ WIDTH - DCR_
DBL_ MASK - DCR_
DBL_ POS - DCR_
DBL_ WIDTH - DIER_
CC1DE_ DISABLED - DIER_
CC1DE_ ENABLED - DIER_
CC1DE_ MASK - DIER_
CC1DE_ POS - DIER_
CC1DE_ WIDTH - DIER_
CC1IE_ DISABLED - DIER_
CC1IE_ ENABLED - DIER_
CC1IE_ MASK - DIER_
CC1IE_ POS - DIER_
CC1IE_ WIDTH - DIER_
CC2DE_ MASK - DIER_
CC2DE_ POS - DIER_
CC2DE_ WIDTH - DIER_
CC2IE_ MASK - DIER_
CC2IE_ POS - DIER_
CC2IE_ WIDTH - DIER_
CC3DE_ MASK - DIER_
CC3DE_ POS - DIER_
CC3DE_ WIDTH - DIER_
CC3IE_ MASK - DIER_
CC3IE_ POS - DIER_
CC3IE_ WIDTH - DIER_
CC4DE_ MASK - DIER_
CC4DE_ POS - DIER_
CC4DE_ WIDTH - DIER_
CC4IE_ MASK - DIER_
CC4IE_ POS - DIER_
CC4IE_ WIDTH - DIER_
TDE_ DISABLED - DIER_
TDE_ ENABLED - DIER_
TDE_ MASK - DIER_
TDE_ POS - DIER_
TDE_ WIDTH - DIER_
TIE_ DISABLED - DIER_
TIE_ ENABLED - DIER_
TIE_ MASK - DIER_
TIE_ POS - DIER_
TIE_ WIDTH - DIER_
UDE_ DISABLED - DIER_
UDE_ ENABLED - DIER_
UDE_ MASK - DIER_
UDE_ POS - DIER_
UDE_ WIDTH - DIER_
UIE_ DISABLED - DIER_
UIE_ ENABLED - DIER_
UIE_ MASK - DIER_
UIE_ POS - DIER_
UIE_ WIDTH - DMAR_
DMAB_ MASK - DMAR_
DMAB_ POS - DMAR_
DMAB_ WIDTH - EGR_
CC1G_ MASK - EGR_
CC1G_ POS - EGR_
CC1G_ TRIGGER - EGR_
CC1G_ WIDTH - EGR_
CC2G_ MASK - EGR_
CC2G_ POS - EGR_
CC2G_ WIDTH - EGR_
CC3G_ MASK - EGR_
CC3G_ POS - EGR_
CC3G_ WIDTH - EGR_
CC4G_ MASK - EGR_
CC4G_ POS - EGR_
CC4G_ WIDTH - EGR_
TG_ MASK - EGR_
TG_ POS - EGR_
TG_ TRIGGER - EGR_
TG_ WIDTH - EGR_
UG_ MASK - EGR_
UG_ POS - EGR_
UG_ UPDATE - EGR_
UG_ WIDTH - OR_
ITR1_ RMP_ MASK - OR_
ITR1_ RMP_ POS - OR_
ITR1_ RMP_ WIDTH - PSC_
PSC_ MASK - PSC_
PSC_ POS - PSC_
PSC_ WIDTH - SMCR_
ECE_ DISABLED - SMCR_
ECE_ ENABLED - SMCR_
ECE_ MASK - SMCR_
ECE_ POS - SMCR_
ECE_ WIDTH - SMCR_
ETF_ FCK_ INT_ N2 - SMCR_
ETF_ FCK_ INT_ N4 - SMCR_
ETF_ FCK_ INT_ N8 - SMCR_
ETF_ FDTS_ DIV2_ N6 - SMCR_
ETF_ FDTS_ DIV2_ N8 - SMCR_
ETF_ FDTS_ DIV4_ N6 - SMCR_
ETF_ FDTS_ DIV4_ N8 - SMCR_
ETF_ FDTS_ DIV8_ N6 - SMCR_
ETF_ FDTS_ DIV8_ N8 - SMCR_
ETF_ FDTS_ DIV16_ N5 - SMCR_
ETF_ FDTS_ DIV16_ N6 - SMCR_
ETF_ FDTS_ DIV16_ N8 - SMCR_
ETF_ FDTS_ DIV32_ N5 - SMCR_
ETF_ FDTS_ DIV32_ N6 - SMCR_
ETF_ FDTS_ DIV32_ N8 - SMCR_
ETF_ MASK - SMCR_
ETF_ NOFILTER - SMCR_
ETF_ POS - SMCR_
ETF_ WIDTH - SMCR_
ETPS_ DIV1 - SMCR_
ETPS_ DIV2 - SMCR_
ETPS_ DIV4 - SMCR_
ETPS_ DIV8 - SMCR_
ETPS_ MASK - SMCR_
ETPS_ POS - SMCR_
ETPS_ WIDTH - SMCR_
ETP_ INVERTED - SMCR_
ETP_ MASK - SMCR_
ETP_ NOTINVERTED - SMCR_
ETP_ POS - SMCR_
ETP_ WIDTH - SMCR_
MSM_ MASK - SMCR_
MSM_ NOSYNC - SMCR_
MSM_ POS - SMCR_
MSM_ SYNC - SMCR_
MSM_ WIDTH - SMCR_
SMS_ DISABLED - SMCR_
SMS_ ENCODER_ MODE_ 1 - SMCR_
SMS_ ENCODER_ MODE_ 2 - SMCR_
SMS_ ENCODER_ MODE_ 3 - SMCR_
SMS_ EXT_ CLOCK_ MODE - SMCR_
SMS_ GATED_ MODE - SMCR_
SMS_ MASK - SMCR_
SMS_ POS - SMCR_
SMS_ RESET_ MODE - SMCR_
SMS_ TRIGGER_ MODE - SMCR_
SMS_ WIDTH - SMCR_
TS_ ETRF - SMCR_
TS_ ITR0 - SMCR_
TS_ ITR1 - SMCR_
TS_ ITR2 - SMCR_
TS_ MASK - SMCR_
TS_ POS - SMCR_
TS_ TI1F P1 - SMCR_
TS_ TI1F_ ED - SMCR_
TS_ TI2F P2 - SMCR_
TS_ WIDTH - SR_
CC1IF_ MASK - SR_
CC1IF_ MATCH - SR_
CC1IF_ POS - SR_
CC1IF_ WIDTH - SR_
CC1OF_ MASK - SR_
CC1OF_ OVERCAPTURE - SR_
CC1OF_ POS - SR_
CC1OF_ WIDTH - SR_
CC2IF_ MASK - SR_
CC2IF_ POS - SR_
CC2IF_ WIDTH - SR_
CC2OF_ MASK - SR_
CC2OF_ POS - SR_
CC2OF_ WIDTH - SR_
CC3IF_ MASK - SR_
CC3IF_ POS - SR_
CC3IF_ WIDTH - SR_
CC3OF_ MASK - SR_
CC3OF_ POS - SR_
CC3OF_ WIDTH - SR_
CC4IF_ MASK - SR_
CC4IF_ POS - SR_
CC4IF_ WIDTH - SR_
CC4OF_ MASK - SR_
CC4OF_ POS - SR_
CC4OF_ WIDTH - SR_
TIF_ MASK - SR_
TIF_ NOTRIGGER - SR_
TIF_ POS - SR_
TIF_ TRIGGER - SR_
TIF_ WIDTH - SR_
UIF_ CLEAR - SR_
UIF_ MASK - SR_
UIF_ POS - SR_
UIF_ UPDATEPENDING - SR_
UIF_ WIDTH