stm32_rust_template/mcu/stm32f407/
timer.rs

1// Timer peripheral definitions
2// Generated from STM32F407 SVD file
3
4use super::{PeripheralAccess, TIM2_BASEADDR, TIM3_BASEADDR, TIM4_BASEADDR, TIM5_BASEADDR};
5
6// Timer Register Block (for general purpose timers TIM2-TIM5)
7#[repr(C)]
8pub struct RegisterBlock {
9    pub cr1: u32,   // RW: control register 1
10    pub cr2: u32,   // RW: control register 2
11    pub smcr: u32,  // RW: slave mode control register
12    pub dier: u32,  // RW: DMA/Interrupt enable register
13    pub sr: u32,    // RW: status register
14    pub egr: u32,   // WO: event generation register
15    pub ccmr1: u32, // RW: capture/compare mode register 1
16    pub ccmr2: u32, // RW: capture/compare mode register 2
17    pub ccer: u32,  // RW: capture/compare enable register
18    pub cnt: u32,   // RW: counter
19    pub psc: u32,   // RW: prescaler
20    pub arr: u32,   // RW: auto-reload register
21    _reserved0: u32,
22    pub ccr1: u32, // RW: capture/compare register 1
23    pub ccr2: u32, // RW: capture/compare register 2
24    pub ccr3: u32, // RW: capture/compare register 3
25    pub ccr4: u32, // RW: capture/compare register 4
26    _reserved1: u32,
27    pub dcr: u32,  // RW: DMA control register
28    pub dmar: u32, // RW: DMA address for full transfer
29    pub or: u32,   // RW: option register
30}
31
32// Timer peripheral instances
33pub struct TIM2;
34pub struct TIM3;
35pub struct TIM4;
36pub struct TIM5;
37
38impl PeripheralAccess for TIM2 {
39    const BASE_ADDRESS: u32 = TIM2_BASEADDR;
40    type RegisterBlock = RegisterBlock;
41}
42
43impl PeripheralAccess for TIM3 {
44    const BASE_ADDRESS: u32 = TIM3_BASEADDR;
45    type RegisterBlock = RegisterBlock;
46}
47
48impl PeripheralAccess for TIM4 {
49    const BASE_ADDRESS: u32 = TIM4_BASEADDR;
50    type RegisterBlock = RegisterBlock;
51}
52
53impl PeripheralAccess for TIM5 {
54    const BASE_ADDRESS: u32 = TIM5_BASEADDR;
55    type RegisterBlock = RegisterBlock;
56}
57
58// Timer Register Field Definitions
59
60// CR1 register fields
61pub const CR1_CKD_POS: u32 = 8;
62pub const CR1_CKD_WIDTH: u32 = 2;
63pub const CR1_CKD_MASK: u32 = 0x3 << 8;
64// CKD enumerated values
65pub const CR1_CKD_DIV1: u32 = 0 << 8;
66pub const CR1_CKD_DIV2: u32 = 1 << 8;
67pub const CR1_CKD_DIV4: u32 = 2 << 8;
68
69pub const CR1_ARPE_POS: u32 = 7;
70pub const CR1_ARPE_WIDTH: u32 = 1;
71pub const CR1_ARPE_MASK: u32 = 0x1 << 7;
72// ARPE enumerated values
73pub const CR1_ARPE_DISABLED: u32 = 0 << 7;
74pub const CR1_ARPE_ENABLED: u32 = 1 << 7;
75
76pub const CR1_CMS_POS: u32 = 5;
77pub const CR1_CMS_WIDTH: u32 = 2;
78pub const CR1_CMS_MASK: u32 = 0x3 << 5;
79// CMS enumerated values
80pub const CR1_CMS_EDGEALIGNED: u32 = 0 << 5;
81pub const CR1_CMS_CENTERALIGNED1: u32 = 1 << 5;
82pub const CR1_CMS_CENTERALIGNED2: u32 = 2 << 5;
83pub const CR1_CMS_CENTERALIGNED3: u32 = 3 << 5;
84
85pub const CR1_DIR_POS: u32 = 4;
86pub const CR1_DIR_WIDTH: u32 = 1;
87pub const CR1_DIR_MASK: u32 = 0x1 << 4;
88// DIR enumerated values
89pub const CR1_DIR_UP: u32 = 0 << 4;
90pub const CR1_DIR_DOWN: u32 = 1 << 4;
91
92pub const CR1_OPM_POS: u32 = 3;
93pub const CR1_OPM_WIDTH: u32 = 1;
94pub const CR1_OPM_MASK: u32 = 0x1 << 3;
95// OPM enumerated values
96pub const CR1_OPM_DISABLED: u32 = 0 << 3;
97pub const CR1_OPM_ENABLED: u32 = 1 << 3;
98
99pub const CR1_URS_POS: u32 = 2;
100pub const CR1_URS_WIDTH: u32 = 1;
101pub const CR1_URS_MASK: u32 = 0x1 << 2;
102// URS enumerated values
103pub const CR1_URS_ANYEVENT: u32 = 0 << 2;
104pub const CR1_URS_COUNTERONLY: u32 = 1 << 2;
105
106pub const CR1_UDIS_POS: u32 = 1;
107pub const CR1_UDIS_WIDTH: u32 = 1;
108pub const CR1_UDIS_MASK: u32 = 0x1 << 1;
109// UDIS enumerated values
110pub const CR1_UDIS_ENABLED: u32 = 0 << 1;
111pub const CR1_UDIS_DISABLED: u32 = 1 << 1;
112
113pub const CR1_CEN_POS: u32 = 0;
114pub const CR1_CEN_WIDTH: u32 = 1;
115pub const CR1_CEN_MASK: u32 = 0x1 << 0;
116// CEN enumerated values
117pub const CR1_CEN_DISABLED: u32 = 0 << 0;
118pub const CR1_CEN_ENABLED: u32 = 1 << 0;
119
120// CR2 register fields
121pub const CR2_TI1S_POS: u32 = 7;
122pub const CR2_TI1S_WIDTH: u32 = 1;
123pub const CR2_TI1S_MASK: u32 = 0x1 << 7;
124// TI1S enumerated values
125pub const CR2_TI1S_NORMAL: u32 = 0 << 7;
126pub const CR2_TI1S_XOR: u32 = 1 << 7;
127
128pub const CR2_MMS_POS: u32 = 4;
129pub const CR2_MMS_WIDTH: u32 = 3;
130pub const CR2_MMS_MASK: u32 = 0x7 << 4;
131// MMS enumerated values
132pub const CR2_MMS_RESET: u32 = 0 << 4;
133pub const CR2_MMS_ENABLE: u32 = 1 << 4;
134pub const CR2_MMS_UPDATE: u32 = 2 << 4;
135pub const CR2_MMS_COMPAREPULSE: u32 = 3 << 4;
136pub const CR2_MMS_COMPAREOC1: u32 = 4 << 4;
137pub const CR2_MMS_COMPAREOC2: u32 = 5 << 4;
138pub const CR2_MMS_COMPAREOC3: u32 = 6 << 4;
139pub const CR2_MMS_COMPAREOC4: u32 = 7 << 4;
140
141pub const CR2_CCDS_POS: u32 = 3;
142pub const CR2_CCDS_WIDTH: u32 = 1;
143pub const CR2_CCDS_MASK: u32 = 0x1 << 3;
144// CCDS enumerated values
145pub const CR2_CCDS_ONCOMPARE: u32 = 0 << 3;
146pub const CR2_CCDS_ONUPDATE: u32 = 1 << 3;
147
148// SMCR register fields
149pub const SMCR_ETP_POS: u32 = 15;
150pub const SMCR_ETP_WIDTH: u32 = 1;
151pub const SMCR_ETP_MASK: u32 = 0x1 << 15;
152// ETP enumerated values
153pub const SMCR_ETP_NOTINVERTED: u32 = 0 << 15;
154pub const SMCR_ETP_INVERTED: u32 = 1 << 15;
155
156pub const SMCR_ECE_POS: u32 = 14;
157pub const SMCR_ECE_WIDTH: u32 = 1;
158pub const SMCR_ECE_MASK: u32 = 0x1 << 14;
159// ECE enumerated values
160pub const SMCR_ECE_DISABLED: u32 = 0 << 14;
161pub const SMCR_ECE_ENABLED: u32 = 1 << 14;
162
163pub const SMCR_ETPS_POS: u32 = 12;
164pub const SMCR_ETPS_WIDTH: u32 = 2;
165pub const SMCR_ETPS_MASK: u32 = 0x3 << 12;
166// ETPS enumerated values
167pub const SMCR_ETPS_DIV1: u32 = 0 << 12;
168pub const SMCR_ETPS_DIV2: u32 = 1 << 12;
169pub const SMCR_ETPS_DIV4: u32 = 2 << 12;
170pub const SMCR_ETPS_DIV8: u32 = 3 << 12;
171
172pub const SMCR_ETF_POS: u32 = 8;
173pub const SMCR_ETF_WIDTH: u32 = 4;
174pub const SMCR_ETF_MASK: u32 = 0xF << 8;
175// ETF enumerated values
176pub const SMCR_ETF_NOFILTER: u32 = 0 << 8;
177pub const SMCR_ETF_FCK_INT_N2: u32 = 1 << 8;
178pub const SMCR_ETF_FCK_INT_N4: u32 = 2 << 8;
179pub const SMCR_ETF_FCK_INT_N8: u32 = 3 << 8;
180pub const SMCR_ETF_FDTS_DIV2_N6: u32 = 4 << 8;
181pub const SMCR_ETF_FDTS_DIV2_N8: u32 = 5 << 8;
182pub const SMCR_ETF_FDTS_DIV4_N6: u32 = 6 << 8;
183pub const SMCR_ETF_FDTS_DIV4_N8: u32 = 7 << 8;
184pub const SMCR_ETF_FDTS_DIV8_N6: u32 = 8 << 8;
185pub const SMCR_ETF_FDTS_DIV8_N8: u32 = 9 << 8;
186pub const SMCR_ETF_FDTS_DIV16_N5: u32 = 10 << 8;
187pub const SMCR_ETF_FDTS_DIV16_N6: u32 = 11 << 8;
188pub const SMCR_ETF_FDTS_DIV16_N8: u32 = 12 << 8;
189pub const SMCR_ETF_FDTS_DIV32_N5: u32 = 13 << 8;
190pub const SMCR_ETF_FDTS_DIV32_N6: u32 = 14 << 8;
191pub const SMCR_ETF_FDTS_DIV32_N8: u32 = 15 << 8;
192
193pub const SMCR_MSM_POS: u32 = 7;
194pub const SMCR_MSM_WIDTH: u32 = 1;
195pub const SMCR_MSM_MASK: u32 = 0x1 << 7;
196// MSM enumerated values
197pub const SMCR_MSM_NOSYNC: u32 = 0 << 7;
198pub const SMCR_MSM_SYNC: u32 = 1 << 7;
199
200pub const SMCR_TS_POS: u32 = 4;
201pub const SMCR_TS_WIDTH: u32 = 3;
202pub const SMCR_TS_MASK: u32 = 0x7 << 4;
203// TS enumerated values
204pub const SMCR_TS_ITR0: u32 = 0 << 4;
205pub const SMCR_TS_ITR1: u32 = 1 << 4;
206pub const SMCR_TS_ITR2: u32 = 2 << 4;
207pub const SMCR_TS_TI1F_ED: u32 = 4 << 4;
208pub const SMCR_TS_TI1FP1: u32 = 5 << 4;
209pub const SMCR_TS_TI2FP2: u32 = 6 << 4;
210pub const SMCR_TS_ETRF: u32 = 7 << 4;
211
212pub const SMCR_SMS_POS: u32 = 0;
213pub const SMCR_SMS_WIDTH: u32 = 3;
214pub const SMCR_SMS_MASK: u32 = 0x7 << 0;
215// SMS enumerated values
216pub const SMCR_SMS_DISABLED: u32 = 0 << 0;
217pub const SMCR_SMS_ENCODER_MODE_1: u32 = 1 << 0;
218pub const SMCR_SMS_ENCODER_MODE_2: u32 = 2 << 0;
219pub const SMCR_SMS_ENCODER_MODE_3: u32 = 3 << 0;
220pub const SMCR_SMS_RESET_MODE: u32 = 4 << 0;
221pub const SMCR_SMS_GATED_MODE: u32 = 5 << 0;
222pub const SMCR_SMS_TRIGGER_MODE: u32 = 6 << 0;
223pub const SMCR_SMS_EXT_CLOCK_MODE: u32 = 7 << 0;
224
225// DIER register fields
226pub const DIER_TDE_POS: u32 = 14;
227pub const DIER_TDE_WIDTH: u32 = 1;
228pub const DIER_TDE_MASK: u32 = 0x1 << 14;
229// TDE enumerated values
230pub const DIER_TDE_DISABLED: u32 = 0 << 14;
231pub const DIER_TDE_ENABLED: u32 = 1 << 14;
232
233pub const DIER_CC4DE_POS: u32 = 12;
234pub const DIER_CC4DE_WIDTH: u32 = 1;
235pub const DIER_CC4DE_MASK: u32 = 0x1 << 12;
236
237pub const DIER_CC3DE_POS: u32 = 11;
238pub const DIER_CC3DE_WIDTH: u32 = 1;
239pub const DIER_CC3DE_MASK: u32 = 0x1 << 11;
240
241pub const DIER_CC2DE_POS: u32 = 10;
242pub const DIER_CC2DE_WIDTH: u32 = 1;
243pub const DIER_CC2DE_MASK: u32 = 0x1 << 10;
244
245pub const DIER_CC1DE_POS: u32 = 9;
246pub const DIER_CC1DE_WIDTH: u32 = 1;
247pub const DIER_CC1DE_MASK: u32 = 0x1 << 9;
248// CC1DE enumerated values
249pub const DIER_CC1DE_DISABLED: u32 = 0 << 9;
250pub const DIER_CC1DE_ENABLED: u32 = 1 << 9;
251
252pub const DIER_UDE_POS: u32 = 8;
253pub const DIER_UDE_WIDTH: u32 = 1;
254pub const DIER_UDE_MASK: u32 = 0x1 << 8;
255// UDE enumerated values
256pub const DIER_UDE_DISABLED: u32 = 0 << 8;
257pub const DIER_UDE_ENABLED: u32 = 1 << 8;
258
259pub const DIER_TIE_POS: u32 = 6;
260pub const DIER_TIE_WIDTH: u32 = 1;
261pub const DIER_TIE_MASK: u32 = 0x1 << 6;
262// TIE enumerated values
263pub const DIER_TIE_DISABLED: u32 = 0 << 6;
264pub const DIER_TIE_ENABLED: u32 = 1 << 6;
265
266pub const DIER_CC4IE_POS: u32 = 4;
267pub const DIER_CC4IE_WIDTH: u32 = 1;
268pub const DIER_CC4IE_MASK: u32 = 0x1 << 4;
269
270pub const DIER_CC3IE_POS: u32 = 3;
271pub const DIER_CC3IE_WIDTH: u32 = 1;
272pub const DIER_CC3IE_MASK: u32 = 0x1 << 3;
273
274pub const DIER_CC2IE_POS: u32 = 2;
275pub const DIER_CC2IE_WIDTH: u32 = 1;
276pub const DIER_CC2IE_MASK: u32 = 0x1 << 2;
277
278pub const DIER_CC1IE_POS: u32 = 1;
279pub const DIER_CC1IE_WIDTH: u32 = 1;
280pub const DIER_CC1IE_MASK: u32 = 0x1 << 1;
281// CC1IE enumerated values
282pub const DIER_CC1IE_DISABLED: u32 = 0 << 1;
283pub const DIER_CC1IE_ENABLED: u32 = 1 << 1;
284
285pub const DIER_UIE_POS: u32 = 0;
286pub const DIER_UIE_WIDTH: u32 = 1;
287pub const DIER_UIE_MASK: u32 = 0x1 << 0;
288// UIE enumerated values
289pub const DIER_UIE_DISABLED: u32 = 0 << 0;
290pub const DIER_UIE_ENABLED: u32 = 1 << 0;
291
292// SR register fields
293pub const SR_CC4OF_POS: u32 = 12;
294pub const SR_CC4OF_WIDTH: u32 = 1;
295pub const SR_CC4OF_MASK: u32 = 0x1 << 12;
296
297pub const SR_CC3OF_POS: u32 = 11;
298pub const SR_CC3OF_WIDTH: u32 = 1;
299pub const SR_CC3OF_MASK: u32 = 0x1 << 11;
300
301pub const SR_CC2OF_POS: u32 = 10;
302pub const SR_CC2OF_WIDTH: u32 = 1;
303pub const SR_CC2OF_MASK: u32 = 0x1 << 10;
304
305pub const SR_CC1OF_POS: u32 = 9;
306pub const SR_CC1OF_WIDTH: u32 = 1;
307pub const SR_CC1OF_MASK: u32 = 0x1 << 9;
308// CC1OF enumerated values
309pub const SR_CC1OF_OVERCAPTURE: u32 = 1 << 9;
310
311pub const SR_TIF_POS: u32 = 6;
312pub const SR_TIF_WIDTH: u32 = 1;
313pub const SR_TIF_MASK: u32 = 0x1 << 6;
314// TIF enumerated values
315pub const SR_TIF_NOTRIGGER: u32 = 0 << 6;
316pub const SR_TIF_TRIGGER: u32 = 1 << 6;
317
318pub const SR_CC4IF_POS: u32 = 4;
319pub const SR_CC4IF_WIDTH: u32 = 1;
320pub const SR_CC4IF_MASK: u32 = 0x1 << 4;
321
322pub const SR_CC3IF_POS: u32 = 3;
323pub const SR_CC3IF_WIDTH: u32 = 1;
324pub const SR_CC3IF_MASK: u32 = 0x1 << 3;
325
326pub const SR_CC2IF_POS: u32 = 2;
327pub const SR_CC2IF_WIDTH: u32 = 1;
328pub const SR_CC2IF_MASK: u32 = 0x1 << 2;
329
330pub const SR_CC1IF_POS: u32 = 1;
331pub const SR_CC1IF_WIDTH: u32 = 1;
332pub const SR_CC1IF_MASK: u32 = 0x1 << 1;
333// CC1IF enumerated values
334pub const SR_CC1IF_MATCH: u32 = 1 << 1;
335
336pub const SR_UIF_POS: u32 = 0;
337pub const SR_UIF_WIDTH: u32 = 1;
338pub const SR_UIF_MASK: u32 = 0x1 << 0;
339// UIF enumerated values
340pub const SR_UIF_CLEAR: u32 = 0 << 0;
341pub const SR_UIF_UPDATEPENDING: u32 = 1 << 0;
342
343// EGR register fields
344pub const EGR_TG_POS: u32 = 6;
345pub const EGR_TG_WIDTH: u32 = 1;
346pub const EGR_TG_MASK: u32 = 0x1 << 6;
347// TG enumerated values
348pub const EGR_TG_TRIGGER: u32 = 1 << 6;
349
350pub const EGR_CC4G_POS: u32 = 4;
351pub const EGR_CC4G_WIDTH: u32 = 1;
352pub const EGR_CC4G_MASK: u32 = 0x1 << 4;
353
354pub const EGR_CC3G_POS: u32 = 3;
355pub const EGR_CC3G_WIDTH: u32 = 1;
356pub const EGR_CC3G_MASK: u32 = 0x1 << 3;
357
358pub const EGR_CC2G_POS: u32 = 2;
359pub const EGR_CC2G_WIDTH: u32 = 1;
360pub const EGR_CC2G_MASK: u32 = 0x1 << 2;
361
362pub const EGR_CC1G_POS: u32 = 1;
363pub const EGR_CC1G_WIDTH: u32 = 1;
364pub const EGR_CC1G_MASK: u32 = 0x1 << 1;
365// CC1G enumerated values
366pub const EGR_CC1G_TRIGGER: u32 = 1 << 1;
367
368pub const EGR_UG_POS: u32 = 0;
369pub const EGR_UG_WIDTH: u32 = 1;
370pub const EGR_UG_MASK: u32 = 0x1 << 0;
371// UG enumerated values
372pub const EGR_UG_UPDATE: u32 = 1 << 0;
373
374// CCMR1 register fields (combines output and input modes)
375// Output mode fields
376pub const CCMR1_OC2CE_POS: u32 = 15;
377pub const CCMR1_OC2CE_WIDTH: u32 = 1;
378pub const CCMR1_OC2CE_MASK: u32 = 0x1 << 15;
379
380pub const CCMR1_OC2M_POS: u32 = 12;
381pub const CCMR1_OC2M_WIDTH: u32 = 3;
382pub const CCMR1_OC2M_MASK: u32 = 0x7 << 12;
383
384pub const CCMR1_OC2PE_POS: u32 = 11;
385pub const CCMR1_OC2PE_WIDTH: u32 = 1;
386pub const CCMR1_OC2PE_MASK: u32 = 0x1 << 11;
387// OC2PE enumerated values
388pub const CCMR1_OC2PE_DISABLED: u32 = 0 << 11;
389pub const CCMR1_OC2PE_ENABLED: u32 = 1 << 11;
390
391pub const CCMR1_OC2FE_POS: u32 = 10;
392pub const CCMR1_OC2FE_WIDTH: u32 = 1;
393pub const CCMR1_OC2FE_MASK: u32 = 0x1 << 10;
394
395pub const CCMR1_OC1CE_POS: u32 = 7;
396pub const CCMR1_OC1CE_WIDTH: u32 = 1;
397pub const CCMR1_OC1CE_MASK: u32 = 0x1 << 7;
398
399pub const CCMR1_OC1M_POS: u32 = 4;
400pub const CCMR1_OC1M_WIDTH: u32 = 3;
401pub const CCMR1_OC1M_MASK: u32 = 0x7 << 4;
402// OC1M enumerated values
403pub const CCMR1_OC1M_FROZEN: u32 = 0 << 4;
404pub const CCMR1_OC1M_ACTIVEONMATCH: u32 = 1 << 4;
405pub const CCMR1_OC1M_INACTIVEONMATCH: u32 = 2 << 4;
406pub const CCMR1_OC1M_TOGGLE: u32 = 3 << 4;
407pub const CCMR1_OC1M_FORCEINACTIVE: u32 = 4 << 4;
408pub const CCMR1_OC1M_FORCEACTIVE: u32 = 5 << 4;
409pub const CCMR1_OC1M_PWMMODE1: u32 = 6 << 4;
410pub const CCMR1_OC1M_PWMMODE2: u32 = 7 << 4;
411
412pub const CCMR1_OC1PE_POS: u32 = 3;
413pub const CCMR1_OC1PE_WIDTH: u32 = 1;
414pub const CCMR1_OC1PE_MASK: u32 = 0x1 << 3;
415// OC1PE enumerated values
416pub const CCMR1_OC1PE_DISABLED: u32 = 0 << 3;
417pub const CCMR1_OC1PE_ENABLED: u32 = 1 << 3;
418
419pub const CCMR1_OC1FE_POS: u32 = 2;
420pub const CCMR1_OC1FE_WIDTH: u32 = 1;
421pub const CCMR1_OC1FE_MASK: u32 = 0x1 << 2;
422
423// Input mode fields (same bit positions, different interpretation)
424pub const CCMR1_IC2F_POS: u32 = 12;
425pub const CCMR1_IC2F_WIDTH: u32 = 4;
426pub const CCMR1_IC2F_MASK: u32 = 0xF << 12;
427
428pub const CCMR1_IC2PSC_POS: u32 = 10;
429pub const CCMR1_IC2PSC_WIDTH: u32 = 2;
430pub const CCMR1_IC2PSC_MASK: u32 = 0x3 << 10;
431
432pub const CCMR1_IC1F_POS: u32 = 4;
433pub const CCMR1_IC1F_WIDTH: u32 = 4;
434pub const CCMR1_IC1F_MASK: u32 = 0xF << 4;
435// IC1F enumerated values
436pub const CCMR1_IC1F_NOFILTER: u32 = 0 << 4;
437pub const CCMR1_IC1F_FCK_INT_N2: u32 = 1 << 4;
438pub const CCMR1_IC1F_FCK_INT_N4: u32 = 2 << 4;
439pub const CCMR1_IC1F_FCK_INT_N8: u32 = 3 << 4;
440pub const CCMR1_IC1F_FDTS_DIV2_N6: u32 = 4 << 4;
441pub const CCMR1_IC1F_FDTS_DIV2_N8: u32 = 5 << 4;
442pub const CCMR1_IC1F_FDTS_DIV4_N6: u32 = 6 << 4;
443pub const CCMR1_IC1F_FDTS_DIV4_N8: u32 = 7 << 4;
444pub const CCMR1_IC1F_FDTS_DIV8_N6: u32 = 8 << 4;
445pub const CCMR1_IC1F_FDTS_DIV8_N8: u32 = 9 << 4;
446pub const CCMR1_IC1F_FDTS_DIV16_N5: u32 = 10 << 4;
447pub const CCMR1_IC1F_FDTS_DIV16_N6: u32 = 11 << 4;
448pub const CCMR1_IC1F_FDTS_DIV16_N8: u32 = 12 << 4;
449pub const CCMR1_IC1F_FDTS_DIV32_N5: u32 = 13 << 4;
450pub const CCMR1_IC1F_FDTS_DIV32_N6: u32 = 14 << 4;
451pub const CCMR1_IC1F_FDTS_DIV32_N8: u32 = 15 << 4;
452
453pub const CCMR1_IC1PSC_POS: u32 = 2;
454pub const CCMR1_IC1PSC_WIDTH: u32 = 2;
455pub const CCMR1_IC1PSC_MASK: u32 = 0x3 << 2;
456
457// Common CC2S and CC1S fields for both modes
458pub const CCMR1_CC2S_POS: u32 = 8;
459pub const CCMR1_CC2S_WIDTH: u32 = 2;
460pub const CCMR1_CC2S_MASK: u32 = 0x3 << 8;
461// CC2S enumerated values (output mode)
462pub const CCMR1_CC2S_OUTPUT: u32 = 0 << 8;
463// CC2S enumerated values (input mode)
464pub const CCMR1_CC2S_TI2: u32 = 1 << 8;
465pub const CCMR1_CC2S_TI1: u32 = 2 << 8;
466pub const CCMR1_CC2S_TRC: u32 = 3 << 8;
467
468pub const CCMR1_CC1S_POS: u32 = 0;
469pub const CCMR1_CC1S_WIDTH: u32 = 2;
470pub const CCMR1_CC1S_MASK: u32 = 0x3 << 0;
471// CC1S enumerated values (output mode)
472pub const CCMR1_CC1S_OUTPUT: u32 = 0 << 0;
473// CC1S enumerated values (input mode)
474pub const CCMR1_CC1S_TI1: u32 = 1 << 0;
475pub const CCMR1_CC1S_TI2: u32 = 2 << 0;
476pub const CCMR1_CC1S_TRC: u32 = 3 << 0;
477
478// CCMR2 register fields (combines output and input modes)
479// Output mode fields
480pub const CCMR2_OC4CE_POS: u32 = 15;
481pub const CCMR2_OC4CE_WIDTH: u32 = 1;
482pub const CCMR2_OC4CE_MASK: u32 = 0x1 << 15;
483
484pub const CCMR2_OC4M_POS: u32 = 12;
485pub const CCMR2_OC4M_WIDTH: u32 = 3;
486pub const CCMR2_OC4M_MASK: u32 = 0x7 << 12;
487
488pub const CCMR2_OC4PE_POS: u32 = 11;
489pub const CCMR2_OC4PE_WIDTH: u32 = 1;
490pub const CCMR2_OC4PE_MASK: u32 = 0x1 << 11;
491// OC4PE enumerated values
492pub const CCMR2_OC4PE_DISABLED: u32 = 0 << 11;
493pub const CCMR2_OC4PE_ENABLED: u32 = 1 << 11;
494
495pub const CCMR2_OC4FE_POS: u32 = 10;
496pub const CCMR2_OC4FE_WIDTH: u32 = 1;
497pub const CCMR2_OC4FE_MASK: u32 = 0x1 << 10;
498
499pub const CCMR2_OC3CE_POS: u32 = 7;
500pub const CCMR2_OC3CE_WIDTH: u32 = 1;
501pub const CCMR2_OC3CE_MASK: u32 = 0x1 << 7;
502
503pub const CCMR2_OC3M_POS: u32 = 4;
504pub const CCMR2_OC3M_WIDTH: u32 = 3;
505pub const CCMR2_OC3M_MASK: u32 = 0x7 << 4;
506// OC3M enumerated values
507pub const CCMR2_OC3M_FROZEN: u32 = 0 << 4;
508pub const CCMR2_OC3M_ACTIVEONMATCH: u32 = 1 << 4;
509pub const CCMR2_OC3M_INACTIVEONMATCH: u32 = 2 << 4;
510pub const CCMR2_OC3M_TOGGLE: u32 = 3 << 4;
511pub const CCMR2_OC3M_FORCEINACTIVE: u32 = 4 << 4;
512pub const CCMR2_OC3M_FORCEACTIVE: u32 = 5 << 4;
513pub const CCMR2_OC3M_PWMMODE1: u32 = 6 << 4;
514pub const CCMR2_OC3M_PWMMODE2: u32 = 7 << 4;
515
516pub const CCMR2_OC3PE_POS: u32 = 3;
517pub const CCMR2_OC3PE_WIDTH: u32 = 1;
518pub const CCMR2_OC3PE_MASK: u32 = 0x1 << 3;
519// OC3PE enumerated values
520pub const CCMR2_OC3PE_DISABLED: u32 = 0 << 3;
521pub const CCMR2_OC3PE_ENABLED: u32 = 1 << 3;
522
523pub const CCMR2_OC3FE_POS: u32 = 2;
524pub const CCMR2_OC3FE_WIDTH: u32 = 1;
525pub const CCMR2_OC3FE_MASK: u32 = 0x1 << 2;
526
527// Input mode fields
528pub const CCMR2_IC4F_POS: u32 = 12;
529pub const CCMR2_IC4F_WIDTH: u32 = 4;
530pub const CCMR2_IC4F_MASK: u32 = 0xF << 12;
531
532pub const CCMR2_IC4PSC_POS: u32 = 10;
533pub const CCMR2_IC4PSC_WIDTH: u32 = 2;
534pub const CCMR2_IC4PSC_MASK: u32 = 0x3 << 10;
535
536pub const CCMR2_IC3F_POS: u32 = 4;
537pub const CCMR2_IC3F_WIDTH: u32 = 4;
538pub const CCMR2_IC3F_MASK: u32 = 0xF << 4;
539
540pub const CCMR2_IC3PSC_POS: u32 = 2;
541pub const CCMR2_IC3PSC_WIDTH: u32 = 2;
542pub const CCMR2_IC3PSC_MASK: u32 = 0x3 << 2;
543
544// Common CC4S and CC3S fields
545pub const CCMR2_CC4S_POS: u32 = 8;
546pub const CCMR2_CC4S_WIDTH: u32 = 2;
547pub const CCMR2_CC4S_MASK: u32 = 0x3 << 8;
548// CC4S enumerated values (output mode)
549pub const CCMR2_CC4S_OUTPUT: u32 = 0 << 8;
550// CC4S enumerated values (input mode)
551pub const CCMR2_CC4S_TI4: u32 = 1 << 8;
552pub const CCMR2_CC4S_TI3: u32 = 2 << 8;
553pub const CCMR2_CC4S_TRC: u32 = 3 << 8;
554
555pub const CCMR2_CC3S_POS: u32 = 0;
556pub const CCMR2_CC3S_WIDTH: u32 = 2;
557pub const CCMR2_CC3S_MASK: u32 = 0x3 << 0;
558// CC3S enumerated values (output mode)
559pub const CCMR2_CC3S_OUTPUT: u32 = 0 << 0;
560// CC3S enumerated values (input mode)
561pub const CCMR2_CC3S_TI3: u32 = 1 << 0;
562pub const CCMR2_CC3S_TI4: u32 = 2 << 0;
563pub const CCMR2_CC3S_TRC: u32 = 3 << 0;
564
565// CCER register fields
566pub const CCER_CC4NP_POS: u32 = 15;
567pub const CCER_CC4NP_WIDTH: u32 = 1;
568pub const CCER_CC4NP_MASK: u32 = 0x1 << 15;
569
570pub const CCER_CC4P_POS: u32 = 13;
571pub const CCER_CC4P_WIDTH: u32 = 1;
572pub const CCER_CC4P_MASK: u32 = 0x1 << 13;
573
574pub const CCER_CC4E_POS: u32 = 12;
575pub const CCER_CC4E_WIDTH: u32 = 1;
576pub const CCER_CC4E_MASK: u32 = 0x1 << 12;
577
578pub const CCER_CC3NP_POS: u32 = 11;
579pub const CCER_CC3NP_WIDTH: u32 = 1;
580pub const CCER_CC3NP_MASK: u32 = 0x1 << 11;
581
582pub const CCER_CC3P_POS: u32 = 9;
583pub const CCER_CC3P_WIDTH: u32 = 1;
584pub const CCER_CC3P_MASK: u32 = 0x1 << 9;
585
586pub const CCER_CC3E_POS: u32 = 8;
587pub const CCER_CC3E_WIDTH: u32 = 1;
588pub const CCER_CC3E_MASK: u32 = 0x1 << 8;
589
590pub const CCER_CC2NP_POS: u32 = 7;
591pub const CCER_CC2NP_WIDTH: u32 = 1;
592pub const CCER_CC2NP_MASK: u32 = 0x1 << 7;
593
594pub const CCER_CC2P_POS: u32 = 5;
595pub const CCER_CC2P_WIDTH: u32 = 1;
596pub const CCER_CC2P_MASK: u32 = 0x1 << 5;
597
598pub const CCER_CC2E_POS: u32 = 4;
599pub const CCER_CC2E_WIDTH: u32 = 1;
600pub const CCER_CC2E_MASK: u32 = 0x1 << 4;
601
602pub const CCER_CC1NP_POS: u32 = 3;
603pub const CCER_CC1NP_WIDTH: u32 = 1;
604pub const CCER_CC1NP_MASK: u32 = 0x1 << 3;
605
606pub const CCER_CC1P_POS: u32 = 1;
607pub const CCER_CC1P_WIDTH: u32 = 1;
608pub const CCER_CC1P_MASK: u32 = 0x1 << 1;
609
610pub const CCER_CC1E_POS: u32 = 0;
611pub const CCER_CC1E_WIDTH: u32 = 1;
612pub const CCER_CC1E_MASK: u32 = 0x1 << 0;
613
614// CNT register fields
615pub const CNT_CNT_POS: u32 = 0;
616pub const CNT_CNT_WIDTH: u32 = 32;
617pub const CNT_CNT_MASK: u32 = 0xFFFFFFFF << 0;
618
619// PSC register fields
620pub const PSC_PSC_POS: u32 = 0;
621pub const PSC_PSC_WIDTH: u32 = 16;
622pub const PSC_PSC_MASK: u32 = 0xFFFF << 0;
623
624// ARR register fields
625pub const ARR_ARR_POS: u32 = 0;
626pub const ARR_ARR_WIDTH: u32 = 32;
627pub const ARR_ARR_MASK: u32 = 0xFFFFFFFF << 0;
628
629// CCR register fields
630pub const CCR1_CCR_POS: u32 = 0;
631pub const CCR1_CCR_WIDTH: u32 = 32;
632pub const CCR1_CCR_MASK: u32 = 0xFFFFFFFF << 0;
633
634pub const CCR2_CCR_POS: u32 = 0;
635pub const CCR2_CCR_WIDTH: u32 = 32;
636pub const CCR2_CCR_MASK: u32 = 0xFFFFFFFF << 0;
637
638pub const CCR3_CCR_POS: u32 = 0;
639pub const CCR3_CCR_WIDTH: u32 = 32;
640pub const CCR3_CCR_MASK: u32 = 0xFFFFFFFF << 0;
641
642pub const CCR4_CCR_POS: u32 = 0;
643pub const CCR4_CCR_WIDTH: u32 = 32;
644pub const CCR4_CCR_MASK: u32 = 0xFFFFFFFF << 0;
645
646// DCR register fields
647pub const DCR_DBL_POS: u32 = 8;
648pub const DCR_DBL_WIDTH: u32 = 5;
649pub const DCR_DBL_MASK: u32 = 0x1F << 8;
650
651pub const DCR_DBA_POS: u32 = 0;
652pub const DCR_DBA_WIDTH: u32 = 5;
653pub const DCR_DBA_MASK: u32 = 0x1F << 0;
654
655// DMAR register fields
656pub const DMAR_DMAB_POS: u32 = 0;
657pub const DMAR_DMAB_WIDTH: u32 = 16;
658pub const DMAR_DMAB_MASK: u32 = 0xFFFF << 0;
659
660// OR register fields
661pub const OR_ITR1_RMP_POS: u32 = 10;
662pub const OR_ITR1_RMP_WIDTH: u32 = 2;
663pub const OR_ITR1_RMP_MASK: u32 = 0x3 << 10;
664
665// Timer Direction enumeration
666#[derive(Copy, Clone, Debug, PartialEq)]
667pub enum TimerDirection {
668    Up = 0,
669    Down = 1,
670}
671
672// Helper functions for Timer
673impl RegisterBlock {
674    /// Enable timer
675    pub fn enable(&mut self) {
676        self.cr1 |= CR1_CEN_MASK;
677    }
678
679    /// Disable timer
680    pub fn disable(&mut self) {
681        self.cr1 &= !CR1_CEN_MASK;
682    }
683
684    /// Set direction (up/down counting)
685    pub fn set_direction(&mut self, direction: TimerDirection) {
686        if direction == TimerDirection::Down {
687            self.cr1 |= CR1_DIR_MASK;
688        } else {
689            self.cr1 &= !CR1_DIR_MASK;
690        }
691    }
692
693    /// Set prescaler value
694    pub fn set_prescaler(&mut self, prescaler: u16) {
695        self.psc = prescaler as u32;
696    }
697
698    /// Set auto-reload value
699    pub fn set_auto_reload(&mut self, arr: u32) {
700        self.arr = arr;
701    }
702
703    /// Get current counter value
704    pub fn get_counter(&self) -> u32 {
705        self.cnt
706    }
707
708    /// Set counter value
709    pub fn set_counter(&mut self, value: u32) {
710        self.cnt = value;
711    }
712
713    /// Enable update interrupt
714    pub fn enable_update_interrupt(&mut self) {
715        self.dier |= DIER_UIE_MASK;
716    }
717
718    /// Disable update interrupt
719    pub fn disable_update_interrupt(&mut self) {
720        self.dier &= !DIER_UIE_MASK;
721    }
722
723    /// Check if update interrupt flag is set
724    pub fn is_update_interrupt_pending(&self) -> bool {
725        (self.sr & SR_UIF_MASK) != 0
726    }
727
728    /// Clear update interrupt flag
729    pub fn clear_update_interrupt(&mut self) {
730        self.sr &= !SR_UIF_MASK;
731    }
732
733    /// Generate update event
734    pub fn generate_update(&mut self) {
735        self.egr |= 0x1; // UG bit
736    }
737
738    /// Set capture/compare value for channel 1
739    pub fn set_ccr1(&mut self, value: u32) {
740        self.ccr1 = value;
741    }
742
743    /// Set capture/compare value for channel 2
744    pub fn set_ccr2(&mut self, value: u32) {
745        self.ccr2 = value;
746    }
747
748    /// Set capture/compare value for channel 3
749    pub fn set_ccr3(&mut self, value: u32) {
750        self.ccr3 = value;
751    }
752
753    /// Set capture/compare value for channel 4
754    pub fn set_ccr4(&mut self, value: u32) {
755        self.ccr4 = value;
756    }
757}
stm32_rust_template/mcu/stm32f407/timer.rs

stm32_rust_template/mcu/stm32f407/
timer.rs
