Structs§
Constants§
- CCR_
CCR_ MASK - CCR_
CCR_ POS - CCR_
CCR_ WIDTH - CCR_
DUTY_ DUTY2_ 1 - CCR_
DUTY_ DUTY16_ 9 - CCR_
DUTY_ MASK - CCR_
DUTY_ POS - CCR_
DUTY_ WIDTH - CCR_
F_ S_ FAST - CCR_
F_ S_ MASK - CCR_
F_ S_ POS - CCR_
F_ S_ STANDARD - CCR_
F_ S_ WIDTH - CR1_
ACK_ ACK - CR1_
ACK_ MASK - CR1_
ACK_ NAK - CR1_
ACK_ POS - CR1_
ACK_ WIDTH - CR1_
ALERT_ DRIVE - CR1_
ALERT_ MASK - CR1_
ALERT_ POS - CR1_
ALERT_ RELEASE - CR1_
ALERT_ WIDTH - CR1_
ENARP_ DISABLED - CR1_
ENARP_ ENABLED - CR1_
ENARP_ MASK - CR1_
ENARP_ POS - CR1_
ENARP_ WIDTH - CR1_
ENGC_ DISABLED - CR1_
ENGC_ ENABLED - CR1_
ENGC_ MASK - CR1_
ENGC_ POS - CR1_
ENGC_ WIDTH - CR1_
ENPEC_ DISABLED - CR1_
ENPEC_ ENABLED - CR1_
ENPEC_ MASK - CR1_
ENPEC_ POS - CR1_
ENPEC_ WIDTH - CR1_
NOSTRETCH_ DISABLED - CR1_
NOSTRETCH_ ENABLED - CR1_
NOSTRETCH_ MASK - CR1_
NOSTRETCH_ POS - CR1_
NOSTRETCH_ WIDTH - CR1_
PEC_ DISABLED - CR1_
PEC_ ENABLED - CR1_
PEC_ MASK - CR1_
PEC_ POS - CR1_
PEC_ WIDTH - CR1_
PE_ DISABLED - CR1_
PE_ ENABLED - CR1_
PE_ MASK - CR1_
PE_ POS - CR1_
PE_ WIDTH - CR1_
POS_ CURRENT - CR1_
POS_ MASK - CR1_
POS_ NEXT - CR1_
POS_ POS - CR1_
POS_ WIDTH - CR1_
SMBTYPE_ DEVICE - CR1_
SMBTYPE_ HOST - CR1_
SMBTYPE_ MASK - CR1_
SMBTYPE_ POS - CR1_
SMBTYPE_ WIDTH - CR1_
SMBUS_ I2C - CR1_
SMBUS_ MASK - CR1_
SMBUS_ POS - CR1_
SMBUS_ SMBUS - CR1_
SMBUS_ WIDTH - CR1_
START_ MASK - CR1_
START_ NOSTART - CR1_
START_ POS - CR1_
START_ START - CR1_
START_ WIDTH - CR1_
STOP_ MASK - CR1_
STOP_ NOSTOP - CR1_
STOP_ POS - CR1_
STOP_ STOP - CR1_
STOP_ WIDTH - CR1_
SWRST_ MASK - CR1_
SWRST_ NOTRESET - CR1_
SWRST_ POS - CR1_
SWRST_ RESET - CR1_
SWRST_ WIDTH - CR2_
DMAEN_ DISABLED - CR2_
DMAEN_ ENABLED - CR2_
DMAEN_ MASK - CR2_
DMAEN_ POS - CR2_
DMAEN_ WIDTH - CR2_
FREQ_ MASK - CR2_
FREQ_ POS - CR2_
FREQ_ WIDTH - CR2_
ITBUFEN_ DISABLED - CR2_
ITBUFEN_ ENABLED - CR2_
ITBUFEN_ MASK - CR2_
ITBUFEN_ POS - CR2_
ITBUFEN_ WIDTH - CR2_
ITERREN_ DISABLED - CR2_
ITERREN_ ENABLED - CR2_
ITERREN_ MASK - CR2_
ITERREN_ POS - CR2_
ITERREN_ WIDTH - CR2_
ITEVTEN_ DISABLED - CR2_
ITEVTEN_ ENABLED - CR2_
ITEVTEN_ MASK - CR2_
ITEVTEN_ POS - CR2_
ITEVTEN_ WIDTH - CR2_
LAST_ LAST - CR2_
LAST_ MASK - CR2_
LAST_ NOTLAST - CR2_
LAST_ POS - CR2_
LAST_ WIDTH - DR_
DR_ MASK - DR_
DR_ POS - DR_
DR_ WIDTH - OAR1_
ADDMODE_ ADD7 - OAR1_
ADDMODE_ ADD10 - OAR1_
ADDMODE_ MASK - OAR1_
ADDMODE_ POS - OAR1_
ADDMODE_ WIDTH - OAR1_
ADD_ MASK - OAR1_
ADD_ POS - OAR1_
ADD_ WIDTH - OAR2_
ADD2_ MASK - OAR2_
ADD2_ POS - OAR2_
ADD2_ WIDTH - OAR2_
ENDUAL_ DUAL - OAR2_
ENDUAL_ MASK - OAR2_
ENDUAL_ POS - OAR2_
ENDUAL_ SINGLE - OAR2_
ENDUAL_ WIDTH - SR1_
ADD10_ MASK - SR1_
ADD10_ POS - SR1_
ADD10_ WIDTH - SR1_
ADDR_ MASK - SR1_
ADDR_ MATCH - SR1_
ADDR_ NOTMATCH - SR1_
ADDR_ POS - SR1_
ADDR_ WIDTH - SR1_
AF_ FAILURE - SR1_
AF_ MASK - SR1_
AF_ NOFAILURE - SR1_
AF_ POS - SR1_
AF_ WIDTH - SR1_
ARLO_ LOST - SR1_
ARLO_ MASK - SR1_
ARLO_ NOLOST - SR1_
ARLO_ POS - SR1_
ARLO_ WIDTH - SR1_
BERR_ ERROR - SR1_
BERR_ MASK - SR1_
BERR_ NOERROR - SR1_
BERR_ POS - SR1_
BERR_ WIDTH - SR1_
BTF_ FINISHED - SR1_
BTF_ MASK - SR1_
BTF_ NOTFINISHED - SR1_
BTF_ POS - SR1_
BTF_ WIDTH - SR1_
OVR_ MASK - SR1_
OVR_ NOOVERRUN - SR1_
OVR_ OVERRUN - SR1_
OVR_ POS - SR1_
OVR_ WIDTH - SR1_
PECERR_ ERROR - SR1_
PECERR_ MASK - SR1_
PECERR_ NOERROR - SR1_
PECERR_ POS - SR1_
PECERR_ WIDTH - SR1_
RXNE_ EMPTY - SR1_
RXNE_ MASK - SR1_
RXNE_ NOTEMPTY - SR1_
RXNE_ POS - SR1_
RXNE_ WIDTH - SR1_
SB_ MASK - SR1_
SB_ NOSTART - SR1_
SB_ POS - SR1_
SB_ START - SR1_
SB_ WIDTH - SR1_
SMBALERT_ ALERT - SR1_
SMBALERT_ MASK - SR1_
SMBALERT_ NOALERT - SR1_
SMBALERT_ POS - SR1_
SMBALERT_ WIDTH - SR1_
STOPF_ MASK - SR1_
STOPF_ NOSTOP - SR1_
STOPF_ POS - SR1_
STOPF_ STOP - SR1_
STOPF_ WIDTH - SR1_
TIMEOUT_ MASK - SR1_
TIMEOUT_ NOTIMEOUT - SR1_
TIMEOUT_ POS - SR1_
TIMEOUT_ TIMEOUT - SR1_
TIMEOUT_ WIDTH - SR1_
TXE_ EMPTY - SR1_
TXE_ MASK - SR1_
TXE_ NOTEMPTY - SR1_
TXE_ POS - SR1_
TXE_ WIDTH - SR2_
BUSY_ MASK - SR2_
BUSY_ POS - SR2_
BUSY_ WIDTH - SR2_
DUALF_ MASK - SR2_
DUALF_ POS - SR2_
DUALF_ WIDTH - SR2_
GENCALL_ MASK - SR2_
GENCALL_ POS - SR2_
GENCALL_ WIDTH - SR2_
MSL_ MASK - SR2_
MSL_ POS - SR2_
MSL_ WIDTH - SR2_
PEC_ MASK - SR2_
PEC_ POS - SR2_
PEC_ WIDTH - SR2_
SMBDEFAULT_ MASK - SR2_
SMBDEFAULT_ POS - SR2_
SMBDEFAULT_ WIDTH - SR2_
SMBHOST_ MASK - SR2_
SMBHOST_ POS - SR2_
SMBHOST_ WIDTH - SR2_
TRA_ MASK - SR2_
TRA_ POS - SR2_
TRA_ WIDTH - TRISE_
TRISE_ MASK - TRISE_
TRISE_ POS - TRISE_
TRISE_ WIDTH