stm32_rust_template/mcu/stm32f407/
i2c.rs

1// I2C peripheral definitions
2// Generated from STM32F407 SVD file
3
4use super::{I2C1_BASEADDR, I2C2_BASEADDR, I2C3_BASEADDR, PeripheralAccess};
5
6// I2C Register Block
7#[repr(C)]
8pub struct RegisterBlock {
9    pub cr1: u32,   // RW: Control register 1
10    pub cr2: u32,   // RW: Control register 2
11    pub oar1: u32,  // RW: Own address register 1
12    pub oar2: u32,  // RW: Own address register 2
13    pub dr: u32,    // RW: Data register
14    pub sr1: u32,   // RW: Status register 1
15    pub sr2: u32,   // RO: Status register 2
16    pub ccr: u32,   // RW: Clock control register
17    pub trise: u32, // RW: TRISE register
18    pub fltr: u32,  // RW: FLTR register
19}
20
21// I2C peripheral instances
22pub struct I2C1;
23pub struct I2C2;
24pub struct I2C3;
25
26impl PeripheralAccess for I2C1 {
27    const BASE_ADDRESS: u32 = I2C1_BASEADDR;
28    type RegisterBlock = RegisterBlock;
29}
30
31impl PeripheralAccess for I2C2 {
32    const BASE_ADDRESS: u32 = I2C2_BASEADDR;
33    type RegisterBlock = RegisterBlock;
34}
35
36impl PeripheralAccess for I2C3 {
37    const BASE_ADDRESS: u32 = I2C3_BASEADDR;
38    type RegisterBlock = RegisterBlock;
39}
40
41// I2C Register Field Definitions
42
43// CR1 register fields
44pub const CR1_SWRST_POS: u32 = 15;
45pub const CR1_SWRST_WIDTH: u32 = 1;
46pub const CR1_SWRST_MASK: u32 = 0x1 << 15;
47// SWRST enumerated values
48pub const CR1_SWRST_NOTRESET: u32 = 0 << 15;
49pub const CR1_SWRST_RESET: u32 = 1 << 15;
50
51pub const CR1_ALERT_POS: u32 = 13;
52pub const CR1_ALERT_WIDTH: u32 = 1;
53pub const CR1_ALERT_MASK: u32 = 0x1 << 13;
54// ALERT enumerated values
55pub const CR1_ALERT_RELEASE: u32 = 0 << 13;
56pub const CR1_ALERT_DRIVE: u32 = 1 << 13;
57
58pub const CR1_PEC_POS: u32 = 12;
59pub const CR1_PEC_WIDTH: u32 = 1;
60pub const CR1_PEC_MASK: u32 = 0x1 << 12;
61// PEC enumerated values
62pub const CR1_PEC_DISABLED: u32 = 0 << 12;
63pub const CR1_PEC_ENABLED: u32 = 1 << 12;
64
65pub const CR1_POS_POS: u32 = 11;
66pub const CR1_POS_WIDTH: u32 = 1;
67pub const CR1_POS_MASK: u32 = 0x1 << 11;
68// POS enumerated values
69pub const CR1_POS_CURRENT: u32 = 0 << 11;
70pub const CR1_POS_NEXT: u32 = 1 << 11;
71
72pub const CR1_ACK_POS: u32 = 10;
73pub const CR1_ACK_WIDTH: u32 = 1;
74pub const CR1_ACK_MASK: u32 = 0x1 << 10;
75// ACK enumerated values
76pub const CR1_ACK_NAK: u32 = 0 << 10;
77pub const CR1_ACK_ACK: u32 = 1 << 10;
78
79pub const CR1_STOP_POS: u32 = 9;
80pub const CR1_STOP_WIDTH: u32 = 1;
81pub const CR1_STOP_MASK: u32 = 0x1 << 9;
82// STOP enumerated values
83pub const CR1_STOP_NOSTOP: u32 = 0 << 9;
84pub const CR1_STOP_STOP: u32 = 1 << 9;
85
86pub const CR1_START_POS: u32 = 8;
87pub const CR1_START_WIDTH: u32 = 1;
88pub const CR1_START_MASK: u32 = 0x1 << 8;
89// START enumerated values
90pub const CR1_START_NOSTART: u32 = 0 << 8;
91pub const CR1_START_START: u32 = 1 << 8;
92
93pub const CR1_NOSTRETCH_POS: u32 = 7;
94pub const CR1_NOSTRETCH_WIDTH: u32 = 1;
95pub const CR1_NOSTRETCH_MASK: u32 = 0x1 << 7;
96// NOSTRETCH enumerated values
97pub const CR1_NOSTRETCH_ENABLED: u32 = 0 << 7;
98pub const CR1_NOSTRETCH_DISABLED: u32 = 1 << 7;
99
100pub const CR1_ENGC_POS: u32 = 6;
101pub const CR1_ENGC_WIDTH: u32 = 1;
102pub const CR1_ENGC_MASK: u32 = 0x1 << 6;
103// ENGC enumerated values
104pub const CR1_ENGC_DISABLED: u32 = 0 << 6;
105pub const CR1_ENGC_ENABLED: u32 = 1 << 6;
106
107pub const CR1_ENPEC_POS: u32 = 5;
108pub const CR1_ENPEC_WIDTH: u32 = 1;
109pub const CR1_ENPEC_MASK: u32 = 0x1 << 5;
110// ENPEC enumerated values
111pub const CR1_ENPEC_DISABLED: u32 = 0 << 5;
112pub const CR1_ENPEC_ENABLED: u32 = 1 << 5;
113
114pub const CR1_ENARP_POS: u32 = 4;
115pub const CR1_ENARP_WIDTH: u32 = 1;
116pub const CR1_ENARP_MASK: u32 = 0x1 << 4;
117// ENARP enumerated values
118pub const CR1_ENARP_DISABLED: u32 = 0 << 4;
119pub const CR1_ENARP_ENABLED: u32 = 1 << 4;
120
121pub const CR1_SMBTYPE_POS: u32 = 3;
122pub const CR1_SMBTYPE_WIDTH: u32 = 1;
123pub const CR1_SMBTYPE_MASK: u32 = 0x1 << 3;
124// SMBTYPE enumerated values
125pub const CR1_SMBTYPE_DEVICE: u32 = 0 << 3;
126pub const CR1_SMBTYPE_HOST: u32 = 1 << 3;
127
128pub const CR1_SMBUS_POS: u32 = 1;
129pub const CR1_SMBUS_WIDTH: u32 = 1;
130pub const CR1_SMBUS_MASK: u32 = 0x1 << 1;
131// SMBUS enumerated values
132pub const CR1_SMBUS_I2C: u32 = 0 << 1;
133pub const CR1_SMBUS_SMBUS: u32 = 1 << 1;
134
135pub const CR1_PE_POS: u32 = 0;
136pub const CR1_PE_WIDTH: u32 = 1;
137pub const CR1_PE_MASK: u32 = 0x1 << 0;
138// PE enumerated values
139pub const CR1_PE_DISABLED: u32 = 0 << 0;
140pub const CR1_PE_ENABLED: u32 = 1 << 0;
141
142// CR2 register fields
143pub const CR2_LAST_POS: u32 = 12;
144pub const CR2_LAST_WIDTH: u32 = 1;
145pub const CR2_LAST_MASK: u32 = 0x1 << 12;
146// LAST enumerated values
147pub const CR2_LAST_NOTLAST: u32 = 0 << 12;
148pub const CR2_LAST_LAST: u32 = 1 << 12;
149
150pub const CR2_DMAEN_POS: u32 = 11;
151pub const CR2_DMAEN_WIDTH: u32 = 1;
152pub const CR2_DMAEN_MASK: u32 = 0x1 << 11;
153// DMAEN enumerated values
154pub const CR2_DMAEN_DISABLED: u32 = 0 << 11;
155pub const CR2_DMAEN_ENABLED: u32 = 1 << 11;
156
157pub const CR2_ITBUFEN_POS: u32 = 10;
158pub const CR2_ITBUFEN_WIDTH: u32 = 1;
159pub const CR2_ITBUFEN_MASK: u32 = 0x1 << 10;
160// ITBUFEN enumerated values
161pub const CR2_ITBUFEN_DISABLED: u32 = 0 << 10;
162pub const CR2_ITBUFEN_ENABLED: u32 = 1 << 10;
163
164pub const CR2_ITEVTEN_POS: u32 = 9;
165pub const CR2_ITEVTEN_WIDTH: u32 = 1;
166pub const CR2_ITEVTEN_MASK: u32 = 0x1 << 9;
167// ITEVTEN enumerated values
168pub const CR2_ITEVTEN_DISABLED: u32 = 0 << 9;
169pub const CR2_ITEVTEN_ENABLED: u32 = 1 << 9;
170
171pub const CR2_ITERREN_POS: u32 = 8;
172pub const CR2_ITERREN_WIDTH: u32 = 1;
173pub const CR2_ITERREN_MASK: u32 = 0x1 << 8;
174// ITERREN enumerated values
175pub const CR2_ITERREN_DISABLED: u32 = 0 << 8;
176pub const CR2_ITERREN_ENABLED: u32 = 1 << 8;
177
178pub const CR2_FREQ_POS: u32 = 0;
179pub const CR2_FREQ_WIDTH: u32 = 6;
180pub const CR2_FREQ_MASK: u32 = 0x3F << 0;
181
182// OAR1 register fields
183pub const OAR1_ADDMODE_POS: u32 = 15;
184pub const OAR1_ADDMODE_WIDTH: u32 = 1;
185pub const OAR1_ADDMODE_MASK: u32 = 0x1 << 15;
186// ADDMODE enumerated values
187pub const OAR1_ADDMODE_ADD7: u32 = 0 << 15;
188pub const OAR1_ADDMODE_ADD10: u32 = 1 << 15;
189
190pub const OAR1_ADD_POS: u32 = 0;
191pub const OAR1_ADD_WIDTH: u32 = 10;
192pub const OAR1_ADD_MASK: u32 = 0x3FF << 0;
193
194// OAR2 register fields
195pub const OAR2_ADD2_POS: u32 = 1;
196pub const OAR2_ADD2_WIDTH: u32 = 7;
197pub const OAR2_ADD2_MASK: u32 = 0x7F << 1;
198
199pub const OAR2_ENDUAL_POS: u32 = 0;
200pub const OAR2_ENDUAL_WIDTH: u32 = 1;
201pub const OAR2_ENDUAL_MASK: u32 = 0x1 << 0;
202// ENDUAL enumerated values
203pub const OAR2_ENDUAL_SINGLE: u32 = 0 << 0;
204pub const OAR2_ENDUAL_DUAL: u32 = 1 << 0;
205
206// DR register fields
207pub const DR_DR_POS: u32 = 0;
208pub const DR_DR_WIDTH: u32 = 8;
209pub const DR_DR_MASK: u32 = 0xFF << 0;
210
211// SR1 register fields
212pub const SR1_SMBALERT_POS: u32 = 15;
213pub const SR1_SMBALERT_WIDTH: u32 = 1;
214pub const SR1_SMBALERT_MASK: u32 = 0x1 << 15;
215// SMBALERT enumerated values
216pub const SR1_SMBALERT_NOALERT: u32 = 0 << 15;
217pub const SR1_SMBALERT_ALERT: u32 = 1 << 15;
218
219pub const SR1_TIMEOUT_POS: u32 = 14;
220pub const SR1_TIMEOUT_WIDTH: u32 = 1;
221pub const SR1_TIMEOUT_MASK: u32 = 0x1 << 14;
222// TIMEOUT enumerated values
223pub const SR1_TIMEOUT_NOTIMEOUT: u32 = 0 << 14;
224pub const SR1_TIMEOUT_TIMEOUT: u32 = 1 << 14;
225
226pub const SR1_PECERR_POS: u32 = 12;
227pub const SR1_PECERR_WIDTH: u32 = 1;
228pub const SR1_PECERR_MASK: u32 = 0x1 << 12;
229// PECERR enumerated values
230pub const SR1_PECERR_NOERROR: u32 = 0 << 12;
231pub const SR1_PECERR_ERROR: u32 = 1 << 12;
232
233pub const SR1_OVR_POS: u32 = 11;
234pub const SR1_OVR_WIDTH: u32 = 1;
235pub const SR1_OVR_MASK: u32 = 0x1 << 11;
236// OVR enumerated values
237pub const SR1_OVR_NOOVERRUN: u32 = 0 << 11;
238pub const SR1_OVR_OVERRUN: u32 = 1 << 11;
239
240pub const SR1_AF_POS: u32 = 10;
241pub const SR1_AF_WIDTH: u32 = 1;
242pub const SR1_AF_MASK: u32 = 0x1 << 10;
243// AF enumerated values
244pub const SR1_AF_NOFAILURE: u32 = 0 << 10;
245pub const SR1_AF_FAILURE: u32 = 1 << 10;
246
247pub const SR1_ARLO_POS: u32 = 9;
248pub const SR1_ARLO_WIDTH: u32 = 1;
249pub const SR1_ARLO_MASK: u32 = 0x1 << 9;
250// ARLO enumerated values
251pub const SR1_ARLO_NOLOST: u32 = 0 << 9;
252pub const SR1_ARLO_LOST: u32 = 1 << 9;
253
254pub const SR1_BERR_POS: u32 = 8;
255pub const SR1_BERR_WIDTH: u32 = 1;
256pub const SR1_BERR_MASK: u32 = 0x1 << 8;
257// BERR enumerated values
258pub const SR1_BERR_NOERROR: u32 = 0 << 8;
259pub const SR1_BERR_ERROR: u32 = 1 << 8;
260
261pub const SR1_TXE_POS: u32 = 7;
262pub const SR1_TXE_WIDTH: u32 = 1;
263pub const SR1_TXE_MASK: u32 = 0x1 << 7;
264// TXE enumerated values
265pub const SR1_TXE_NOTEMPTY: u32 = 0 << 7;
266pub const SR1_TXE_EMPTY: u32 = 1 << 7;
267
268pub const SR1_RXNE_POS: u32 = 6;
269pub const SR1_RXNE_WIDTH: u32 = 1;
270pub const SR1_RXNE_MASK: u32 = 0x1 << 6;
271// RXNE enumerated values
272pub const SR1_RXNE_EMPTY: u32 = 0 << 6;
273pub const SR1_RXNE_NOTEMPTY: u32 = 1 << 6;
274
275pub const SR1_STOPF_POS: u32 = 4;
276pub const SR1_STOPF_WIDTH: u32 = 1;
277pub const SR1_STOPF_MASK: u32 = 0x1 << 4;
278// STOPF enumerated values
279pub const SR1_STOPF_NOSTOP: u32 = 0 << 4;
280pub const SR1_STOPF_STOP: u32 = 1 << 4;
281
282pub const SR1_ADD10_POS: u32 = 3;
283pub const SR1_ADD10_WIDTH: u32 = 1;
284pub const SR1_ADD10_MASK: u32 = 0x1 << 3;
285
286pub const SR1_BTF_POS: u32 = 2;
287pub const SR1_BTF_WIDTH: u32 = 1;
288pub const SR1_BTF_MASK: u32 = 0x1 << 2;
289// BTF enumerated values
290pub const SR1_BTF_NOTFINISHED: u32 = 0 << 2;
291pub const SR1_BTF_FINISHED: u32 = 1 << 2;
292
293pub const SR1_ADDR_POS: u32 = 1;
294pub const SR1_ADDR_WIDTH: u32 = 1;
295pub const SR1_ADDR_MASK: u32 = 0x1 << 1;
296// ADDR enumerated values
297pub const SR1_ADDR_NOTMATCH: u32 = 0 << 1;
298pub const SR1_ADDR_MATCH: u32 = 1 << 1;
299
300pub const SR1_SB_POS: u32 = 0;
301pub const SR1_SB_WIDTH: u32 = 1;
302pub const SR1_SB_MASK: u32 = 0x1 << 0;
303// SB enumerated values
304pub const SR1_SB_NOSTART: u32 = 0 << 0;
305pub const SR1_SB_START: u32 = 1 << 0;
306
307// SR2 register fields
308pub const SR2_PEC_POS: u32 = 8;
309pub const SR2_PEC_WIDTH: u32 = 8;
310pub const SR2_PEC_MASK: u32 = 0xFF << 8;
311
312pub const SR2_DUALF_POS: u32 = 7;
313pub const SR2_DUALF_WIDTH: u32 = 1;
314pub const SR2_DUALF_MASK: u32 = 0x1 << 7;
315
316pub const SR2_SMBHOST_POS: u32 = 6;
317pub const SR2_SMBHOST_WIDTH: u32 = 1;
318pub const SR2_SMBHOST_MASK: u32 = 0x1 << 6;
319
320pub const SR2_SMBDEFAULT_POS: u32 = 5;
321pub const SR2_SMBDEFAULT_WIDTH: u32 = 1;
322pub const SR2_SMBDEFAULT_MASK: u32 = 0x1 << 5;
323
324pub const SR2_GENCALL_POS: u32 = 4;
325pub const SR2_GENCALL_WIDTH: u32 = 1;
326pub const SR2_GENCALL_MASK: u32 = 0x1 << 4;
327
328pub const SR2_TRA_POS: u32 = 2;
329pub const SR2_TRA_WIDTH: u32 = 1;
330pub const SR2_TRA_MASK: u32 = 0x1 << 2;
331
332pub const SR2_BUSY_POS: u32 = 1;
333pub const SR2_BUSY_WIDTH: u32 = 1;
334pub const SR2_BUSY_MASK: u32 = 0x1 << 1;
335
336pub const SR2_MSL_POS: u32 = 0;
337pub const SR2_MSL_WIDTH: u32 = 1;
338pub const SR2_MSL_MASK: u32 = 0x1 << 0;
339
340// CCR register fields
341pub const CCR_F_S_POS: u32 = 15;
342pub const CCR_F_S_WIDTH: u32 = 1;
343pub const CCR_F_S_MASK: u32 = 0x1 << 15;
344// F_S enumerated values
345pub const CCR_F_S_STANDARD: u32 = 0 << 15;
346pub const CCR_F_S_FAST: u32 = 1 << 15;
347
348pub const CCR_DUTY_POS: u32 = 14;
349pub const CCR_DUTY_WIDTH: u32 = 1;
350pub const CCR_DUTY_MASK: u32 = 0x1 << 14;
351// DUTY enumerated values
352pub const CCR_DUTY_DUTY2_1: u32 = 0 << 14;
353pub const CCR_DUTY_DUTY16_9: u32 = 1 << 14;
354
355pub const CCR_CCR_POS: u32 = 0;
356pub const CCR_CCR_WIDTH: u32 = 12;
357pub const CCR_CCR_MASK: u32 = 0xFFF << 0;
358
359// TRISE register fields
360pub const TRISE_TRISE_POS: u32 = 0;
361pub const TRISE_TRISE_WIDTH: u32 = 6;
362pub const TRISE_TRISE_MASK: u32 = 0x3F << 0;
363
364// Helper functions for I2C
365impl RegisterBlock {
366    /// Enable I2C peripheral
367    pub fn enable(&mut self) {
368        self.cr1 |= CR1_PE_MASK;
369    }
370
371    /// Disable I2C peripheral
372    pub fn disable(&mut self) {
373        self.cr1 &= !CR1_PE_MASK;
374    }
375
376    /// Generate START condition
377    pub fn generate_start(&mut self) {
378        self.cr1 |= CR1_START_MASK;
379    }
380
381    /// Generate STOP condition
382    pub fn generate_stop(&mut self) {
383        self.cr1 |= CR1_STOP_MASK;
384    }
385
386    /// Enable/disable ACK
387    pub fn set_ack(&mut self, enable: bool) {
388        if enable {
389            self.cr1 |= CR1_ACK_MASK;
390        } else {
391            self.cr1 &= !CR1_ACK_MASK;
392        }
393    }
394
395    /// Check if START bit is sent
396    pub fn is_start_sent(&self) -> bool {
397        (self.sr1 & SR1_SB_MASK) != 0
398    }
399
400    /// Check if address is sent
401    pub fn is_addr_sent(&self) -> bool {
402        (self.sr1 & SR1_ADDR_MASK) != 0
403    }
404
405    /// Check if transmit buffer is empty
406    pub fn is_tx_empty(&self) -> bool {
407        (self.sr1 & SR1_TXE_MASK) != 0
408    }
409
410    /// Check if receive buffer is not empty
411    pub fn is_rx_not_empty(&self) -> bool {
412        (self.sr1 & SR1_RXNE_MASK) != 0
413    }
414
415    /// Check if byte transfer is finished
416    pub fn is_btf(&self) -> bool {
417        (self.sr1 & SR1_BTF_MASK) != 0
418    }
419
420    /// Check if bus is busy
421    pub fn is_busy(&self) -> bool {
422        (self.sr2 & SR2_BUSY_MASK) != 0
423    }
424
425    /// Write data
426    pub fn write_data(&mut self, data: u8) {
427        self.dr = data as u32;
428    }
429
430    /// Read data
431    pub fn read_data(&self) -> u8 {
432        self.dr as u8
433    }
434
435    /// Clear ADDR flag (read SR1 then SR2)
436    pub fn clear_addr_flag(&self) {
437        let _ = self.sr1;
438        let _ = self.sr2;
439    }
440
441    /// Set I2C clock frequency (in MHz)
442    pub fn set_clock_freq(&mut self, freq_mhz: u8) {
443        self.cr2 = (self.cr2 & !0x3F) | (freq_mhz as u32 & 0x3F);
444    }
445}
stm32_rust_template/mcu/stm32f407/i2c.rs

stm32_rust_template/mcu/stm32f407/
i2c.rs
