Structs§
Enums§
Constants§
- CR1_
AWDCH_ MASK - CR1_
AWDCH_ POS - CR1_
AWDCH_ WIDTH - CR1_
AWDEN_ DISABLED - CR1_
AWDEN_ ENABLED - CR1_
AWDEN_ MASK - CR1_
AWDEN_ POS - CR1_
AWDEN_ WIDTH - CR1_
AWDIE_ DISABLED - CR1_
AWDIE_ ENABLED - CR1_
AWDIE_ MASK - CR1_
AWDIE_ POS - CR1_
AWDIE_ WIDTH - CR1_
AWDSGL_ ALLCHANNELS - CR1_
AWDSGL_ MASK - CR1_
AWDSGL_ POS - CR1_
AWDSGL_ SINGLECHANNEL - CR1_
AWDSGL_ WIDTH - CR1_
DISCEN_ DISABLED - CR1_
DISCEN_ ENABLED - CR1_
DISCEN_ MASK - CR1_
DISCEN_ POS - CR1_
DISCEN_ WIDTH - CR1_
DISCNUM_ MASK - CR1_
DISCNUM_ POS - CR1_
DISCNUM_ WIDTH - CR1_
EOCIE_ DISABLED - CR1_
EOCIE_ ENABLED - CR1_
EOCIE_ MASK - CR1_
EOCIE_ POS - CR1_
EOCIE_ WIDTH - CR1_
JAUTO_ DISABLED - CR1_
JAUTO_ ENABLED - CR1_
JAUTO_ MASK - CR1_
JAUTO_ POS - CR1_
JAUTO_ WIDTH - CR1_
JAWDEN_ DISABLED - CR1_
JAWDEN_ ENABLED - CR1_
JAWDEN_ MASK - CR1_
JAWDEN_ POS - CR1_
JAWDEN_ WIDTH - CR1_
JDISCEN_ DISABLED - CR1_
JDISCEN_ ENABLED - CR1_
JDISCEN_ MASK - CR1_
JDISCEN_ POS - CR1_
JDISCEN_ WIDTH - CR1_
JEOCIE_ DISABLED - CR1_
JEOCIE_ ENABLED - CR1_
JEOCIE_ MASK - CR1_
JEOCIE_ POS - CR1_
JEOCIE_ WIDTH - CR1_
OVRIE_ DISABLED - CR1_
OVRIE_ ENABLED - CR1_
OVRIE_ MASK - CR1_
OVRIE_ POS - CR1_
OVRIE_ WIDTH - CR1_
RES_ EIGHTBIT - CR1_
RES_ MASK - CR1_
RES_ POS - CR1_
RES_ SIXBIT - CR1_
RES_ TENBIT - CR1_
RES_ TWELVEBIT - CR1_
RES_ WIDTH - CR1_
SCAN_ DISABLED - CR1_
SCAN_ ENABLED - CR1_
SCAN_ MASK - CR1_
SCAN_ POS - CR1_
SCAN_ WIDTH - CR2_
ADON_ DISABLED - CR2_
ADON_ ENABLED - CR2_
ADON_ MASK - CR2_
ADON_ POS - CR2_
ADON_ WIDTH - CR2_
ALIGN_ LEFT - CR2_
ALIGN_ MASK - CR2_
ALIGN_ POS - CR2_
ALIGN_ RIGHT - CR2_
ALIGN_ WIDTH - CR2_
CONT_ CONTINUOUS - CR2_
CONT_ MASK - CR2_
CONT_ POS - CR2_
CONT_ SINGLE - CR2_
CONT_ WIDTH - CR2_
DDS_ CONTINUOUS - CR2_
DDS_ MASK - CR2_
DDS_ POS - CR2_
DDS_ SINGLE - CR2_
DDS_ WIDTH - CR2_
DMA_ DISABLED - CR2_
DMA_ ENABLED - CR2_
DMA_ MASK - CR2_
DMA_ POS - CR2_
DMA_ WIDTH - CR2_
EOCS_ EACHCONVERSION - CR2_
EOCS_ EACHSEQUENCE - CR2_
EOCS_ MASK - CR2_
EOCS_ POS - CR2_
EOCS_ WIDTH - CR2_
EXTEN_ BOTHEDGES - CR2_
EXTEN_ DISABLED - CR2_
EXTEN_ FALLINGEDGE - CR2_
EXTEN_ MASK - CR2_
EXTEN_ POS - CR2_
EXTEN_ RISINGEDGE - CR2_
EXTEN_ WIDTH - CR2_
EXTSEL_ MASK - CR2_
EXTSEL_ POS - CR2_
EXTSEL_ TIM1C C1 - CR2_
EXTSEL_ TIM1C C2 - CR2_
EXTSEL_ TIM1C C3 - CR2_
EXTSEL_ TIM2C C2 - CR2_
EXTSEL_ TIM2C C3 - CR2_
EXTSEL_ TIM2C C4 - CR2_
EXTSEL_ TIM2TRGO - CR2_
EXTSEL_ WIDTH - CR2_
JEXTEN_ BOTHEDGES - CR2_
JEXTEN_ DISABLED - CR2_
JEXTEN_ FALLINGEDGE - CR2_
JEXTEN_ MASK - CR2_
JEXTEN_ POS - CR2_
JEXTEN_ RISINGEDGE - CR2_
JEXTEN_ WIDTH - CR2_
JEXTSEL_ MASK - CR2_
JEXTSEL_ POS - CR2_
JEXTSEL_ TIM1C C4 - CR2_
JEXTSEL_ TIM1TRGO - CR2_
JEXTSEL_ TIM1TRG O2 - CR2_
JEXTSEL_ TIM2C C1 - CR2_
JEXTSEL_ TIM2TRGO - CR2_
JEXTSEL_ TIM3C C1 - CR2_
JEXTSEL_ TIM3C C3 - CR2_
JEXTSEL_ TIM3C C4 - CR2_
JEXTSEL_ TIM4TRGO - CR2_
JEXTSEL_ TIM5TRGO - CR2_
JEXTSEL_ TIM6TRGO - CR2_
JEXTSEL_ TIM8C C4 - CR2_
JEXTSEL_ TIM8TRGO - CR2_
JEXTSEL_ TIM8TRG O2 - CR2_
JEXTSEL_ WIDTH - CR2_
JSWSTART_ MASK - CR2_
JSWSTART_ POS - CR2_
JSWSTART_ START - CR2_
JSWSTART_ WIDTH - CR2_
SWSTART_ MASK - CR2_
SWSTART_ POS - CR2_
SWSTART_ START - CR2_
SWSTART_ WIDTH - DR_
DATA_ MASK - DR_
DATA_ POS - DR_
DATA_ WIDTH - HTR_
HT_ MASK - HTR_
HT_ POS - HTR_
HT_ WIDTH - JDR1_
JDATA_ MASK - JDR1_
JDATA_ POS - JDR1_
JDATA_ WIDTH - JDR2_
JDATA_ MASK - JDR2_
JDATA_ POS - JDR2_
JDATA_ WIDTH - JDR3_
JDATA_ MASK - JDR3_
JDATA_ POS - JDR3_
JDATA_ WIDTH - JDR4_
JDATA_ MASK - JDR4_
JDATA_ POS - JDR4_
JDATA_ WIDTH - JOFR1_
JOFFSET_ MASK - JOFR1_
JOFFSET_ POS - JOFR1_
JOFFSET_ WIDTH - JOFR2_
JOFFSET_ MASK - JOFR2_
JOFFSET_ POS - JOFR2_
JOFFSET_ WIDTH - JOFR3_
JOFFSET_ MASK - JOFR3_
JOFFSET_ POS - JOFR3_
JOFFSET_ WIDTH - JOFR4_
JOFFSET_ MASK - JOFR4_
JOFFSET_ POS - JOFR4_
JOFFSET_ WIDTH - JSQR_
JL_ MASK - JSQR_
JL_ POS - JSQR_
JL_ WIDTH - JSQR_
JSQ1_ MASK - JSQR_
JSQ1_ POS - JSQR_
JSQ1_ WIDTH - JSQR_
JSQ2_ MASK - JSQR_
JSQ2_ POS - JSQR_
JSQ2_ WIDTH - JSQR_
JSQ3_ MASK - JSQR_
JSQ3_ POS - JSQR_
JSQ3_ WIDTH - JSQR_
JSQ4_ MASK - JSQR_
JSQ4_ POS - JSQR_
JSQ4_ WIDTH - LTR_
LT_ MASK - LTR_
LT_ POS - LTR_
LT_ WIDTH - SMPR1_
SMP10_ CYCLE S3 - SMPR1_
SMP10_ CYCLE S15 - SMPR1_
SMP10_ CYCLE S28 - SMPR1_
SMP10_ CYCLE S56 - SMPR1_
SMP10_ CYCLE S84 - SMPR1_
SMP10_ CYCLE S112 - SMPR1_
SMP10_ CYCLE S144 - SMPR1_
SMP10_ CYCLE S480 - SMPR1_
SMP10_ MASK - SMPR1_
SMP10_ POS - SMPR1_
SMP10_ WIDTH - SMPR1_
SMP11_ MASK - SMPR1_
SMP11_ POS - SMPR1_
SMP11_ WIDTH - SMPR1_
SMP12_ MASK - SMPR1_
SMP12_ POS - SMPR1_
SMP12_ WIDTH - SMPR1_
SMP13_ MASK - SMPR1_
SMP13_ POS - SMPR1_
SMP13_ WIDTH - SMPR1_
SMP14_ MASK - SMPR1_
SMP14_ POS - SMPR1_
SMP14_ WIDTH - SMPR1_
SMP15_ MASK - SMPR1_
SMP15_ POS - SMPR1_
SMP15_ WIDTH - SMPR1_
SMP16_ MASK - SMPR1_
SMP16_ POS - SMPR1_
SMP16_ WIDTH - SMPR1_
SMP17_ MASK - SMPR1_
SMP17_ POS - SMPR1_
SMP17_ WIDTH - SMPR1_
SMP18_ MASK - SMPR1_
SMP18_ POS - SMPR1_
SMP18_ WIDTH - SMPR2_
SMP0_ CYCLE S3 - SMPR2_
SMP0_ CYCLE S15 - SMPR2_
SMP0_ CYCLE S28 - SMPR2_
SMP0_ CYCLE S56 - SMPR2_
SMP0_ CYCLE S84 - SMPR2_
SMP0_ CYCLE S112 - SMPR2_
SMP0_ CYCLE S144 - SMPR2_
SMP0_ CYCLE S480 - SMPR2_
SMP0_ MASK - SMPR2_
SMP0_ POS - SMPR2_
SMP0_ WIDTH - SMPR2_
SMP1_ MASK - SMPR2_
SMP1_ POS - SMPR2_
SMP1_ WIDTH - SMPR2_
SMP2_ MASK - SMPR2_
SMP2_ POS - SMPR2_
SMP2_ WIDTH - SMPR2_
SMP3_ MASK - SMPR2_
SMP3_ POS - SMPR2_
SMP3_ WIDTH - SMPR2_
SMP4_ MASK - SMPR2_
SMP4_ POS - SMPR2_
SMP4_ WIDTH - SMPR2_
SMP5_ MASK - SMPR2_
SMP5_ POS - SMPR2_
SMP5_ WIDTH - SMPR2_
SMP6_ MASK - SMPR2_
SMP6_ POS - SMPR2_
SMP6_ WIDTH - SMPR2_
SMP7_ MASK - SMPR2_
SMP7_ POS - SMPR2_
SMP7_ WIDTH - SMPR2_
SMP8_ MASK - SMPR2_
SMP8_ POS - SMPR2_
SMP8_ WIDTH - SMPR2_
SMP9_ MASK - SMPR2_
SMP9_ POS - SMPR2_
SMP9_ WIDTH - SQR1_
L_ MASK - SQR1_
L_ POS - SQR1_
L_ WIDTH - SQR1_
SQ13_ MASK - SQR1_
SQ13_ POS - SQR1_
SQ13_ WIDTH - SQR1_
SQ14_ MASK - SQR1_
SQ14_ POS - SQR1_
SQ14_ WIDTH - SQR1_
SQ15_ MASK - SQR1_
SQ15_ POS - SQR1_
SQ15_ WIDTH - SQR1_
SQ16_ MASK - SQR1_
SQ16_ POS - SQR1_
SQ16_ WIDTH - SQR2_
SQ7_ MASK - SQR2_
SQ7_ POS - SQR2_
SQ7_ WIDTH - SQR2_
SQ8_ MASK - SQR2_
SQ8_ POS - SQR2_
SQ8_ WIDTH - SQR2_
SQ9_ MASK - SQR2_
SQ9_ POS - SQR2_
SQ9_ WIDTH - SQR2_
SQ10_ MASK - SQR2_
SQ10_ POS - SQR2_
SQ10_ WIDTH - SQR2_
SQ11_ MASK - SQR2_
SQ11_ POS - SQR2_
SQ11_ WIDTH - SQR2_
SQ12_ MASK - SQR2_
SQ12_ POS - SQR2_
SQ12_ WIDTH - SQR3_
SQ1_ MASK - SQR3_
SQ1_ POS - SQR3_
SQ1_ WIDTH - SQR3_
SQ2_ MASK - SQR3_
SQ2_ POS - SQR3_
SQ2_ WIDTH - SQR3_
SQ3_ MASK - SQR3_
SQ3_ POS - SQR3_
SQ3_ WIDTH - SQR3_
SQ4_ MASK - SQR3_
SQ4_ POS - SQR3_
SQ4_ WIDTH - SQR3_
SQ5_ MASK - SQR3_
SQ5_ POS - SQR3_
SQ5_ WIDTH - SQR3_
SQ6_ MASK - SQR3_
SQ6_ POS - SQR3_
SQ6_ WIDTH - SR_
AWD_ EVENT - SR_
AWD_ MASK - SR_
AWD_ NOEVENT - SR_
AWD_ POS - SR_
AWD_ WIDTH - SR_
EOC_ COMPLETE - SR_
EOC_ MASK - SR_
EOC_ NOTCOMPLETE - SR_
EOC_ POS - SR_
EOC_ WIDTH - SR_
JEOC_ COMPLETE - SR_
JEOC_ MASK - SR_
JEOC_ NOTCOMPLETE - SR_
JEOC_ POS - SR_
JEOC_ WIDTH - SR_
JSTRT_ MASK - SR_
JSTRT_ NOTSTARTED - SR_
JSTRT_ POS - SR_
JSTRT_ STARTED - SR_
JSTRT_ WIDTH - SR_
OVR_ MASK - SR_
OVR_ NOOVERRUN - SR_
OVR_ OVERRUN - SR_
OVR_ POS - SR_
OVR_ WIDTH - SR_
STRT_ MASK - SR_
STRT_ NOTSTARTED - SR_
STRT_ POS - SR_
STRT_ STARTED - SR_
STRT_ WIDTH