stm32_rust_template/mcu/stm32f407/
adc.rs

1// ADC peripheral definitions
2// Generated from STM32F407 SVD file
3
4use super::{ADC1_BASEADDR, ADC2_BASEADDR, ADC3_BASEADDR, PeripheralAccess};
5
6// ADC Register Block
7#[repr(C)]
8pub struct RegisterBlock {
9    pub sr: u32,    // RW: status register
10    pub cr1: u32,   // RW: control register 1
11    pub cr2: u32,   // RW: control register 2
12    pub smpr1: u32, // RW: sample time register 1
13    pub smpr2: u32, // RW: sample time register 2
14    pub jofr1: u32, // RW: injected channel data offset register x
15    pub jofr2: u32, // RW: injected channel data offset register x
16    pub jofr3: u32, // RW: injected channel data offset register x
17    pub jofr4: u32, // RW: injected channel data offset register x
18    pub htr: u32,   // RW: watchdog higher threshold register
19    pub ltr: u32,   // RW: watchdog lower threshold register
20    pub sqr1: u32,  // RW: regular sequence register 1
21    pub sqr2: u32,  // RW: regular sequence register 2
22    pub sqr3: u32,  // RW: regular sequence register 3
23    pub jsqr: u32,  // RW: injected sequence register
24    pub jdr1: u32,  // RO: injected data register x
25    pub jdr2: u32,  // RO: injected data register x
26    pub jdr3: u32,  // RO: injected data register x
27    pub jdr4: u32,  // RO: injected data register x
28    pub dr: u32,    // RO: regular data register
29}
30
31// ADC peripheral instances
32pub struct ADC1;
33pub struct ADC2;
34pub struct ADC3;
35
36impl PeripheralAccess for ADC1 {
37    const BASE_ADDRESS: u32 = ADC1_BASEADDR;
38    type RegisterBlock = RegisterBlock;
39}
40
41impl PeripheralAccess for ADC2 {
42    const BASE_ADDRESS: u32 = ADC2_BASEADDR;
43    type RegisterBlock = RegisterBlock;
44}
45
46impl PeripheralAccess for ADC3 {
47    const BASE_ADDRESS: u32 = ADC3_BASEADDR;
48    type RegisterBlock = RegisterBlock;
49}
50
51// ADC Register Field Definitions
52
53// SR register fields
54pub const SR_OVR_POS: u32 = 5;
55pub const SR_OVR_WIDTH: u32 = 1;
56pub const SR_OVR_MASK: u32 = 0x1 << 5;
57// OVR enumerated values
58pub const SR_OVR_NOOVERRUN: u32 = 0 << 5;
59pub const SR_OVR_OVERRUN: u32 = 1 << 5;
60
61pub const SR_STRT_POS: u32 = 4;
62pub const SR_STRT_WIDTH: u32 = 1;
63pub const SR_STRT_MASK: u32 = 0x1 << 4;
64// STRT enumerated values
65pub const SR_STRT_NOTSTARTED: u32 = 0 << 4;
66pub const SR_STRT_STARTED: u32 = 1 << 4;
67
68pub const SR_JSTRT_POS: u32 = 3;
69pub const SR_JSTRT_WIDTH: u32 = 1;
70pub const SR_JSTRT_MASK: u32 = 0x1 << 3;
71// JSTRT enumerated values
72pub const SR_JSTRT_NOTSTARTED: u32 = 0 << 3;
73pub const SR_JSTRT_STARTED: u32 = 1 << 3;
74
75pub const SR_JEOC_POS: u32 = 2;
76pub const SR_JEOC_WIDTH: u32 = 1;
77pub const SR_JEOC_MASK: u32 = 0x1 << 2;
78// JEOC enumerated values
79pub const SR_JEOC_NOTCOMPLETE: u32 = 0 << 2;
80pub const SR_JEOC_COMPLETE: u32 = 1 << 2;
81
82pub const SR_EOC_POS: u32 = 1;
83pub const SR_EOC_WIDTH: u32 = 1;
84pub const SR_EOC_MASK: u32 = 0x1 << 1;
85// EOC enumerated values
86pub const SR_EOC_NOTCOMPLETE: u32 = 0 << 1;
87pub const SR_EOC_COMPLETE: u32 = 1 << 1;
88
89pub const SR_AWD_POS: u32 = 0;
90pub const SR_AWD_WIDTH: u32 = 1;
91pub const SR_AWD_MASK: u32 = 0x1 << 0;
92// AWD enumerated values
93pub const SR_AWD_NOEVENT: u32 = 0 << 0;
94pub const SR_AWD_EVENT: u32 = 1 << 0;
95
96// CR1 register fields
97pub const CR1_OVRIE_POS: u32 = 26;
98pub const CR1_OVRIE_WIDTH: u32 = 1;
99pub const CR1_OVRIE_MASK: u32 = 0x1 << 26;
100// OVRIE enumerated values
101pub const CR1_OVRIE_DISABLED: u32 = 0 << 26;
102pub const CR1_OVRIE_ENABLED: u32 = 1 << 26;
103
104pub const CR1_RES_POS: u32 = 24;
105pub const CR1_RES_WIDTH: u32 = 2;
106pub const CR1_RES_MASK: u32 = 0x3 << 24;
107// RES enumerated values
108pub const CR1_RES_TWELVEBIT: u32 = 0 << 24;
109pub const CR1_RES_TENBIT: u32 = 1 << 24;
110pub const CR1_RES_EIGHTBIT: u32 = 2 << 24;
111pub const CR1_RES_SIXBIT: u32 = 3 << 24;
112
113pub const CR1_AWDEN_POS: u32 = 23;
114pub const CR1_AWDEN_WIDTH: u32 = 1;
115pub const CR1_AWDEN_MASK: u32 = 0x1 << 23;
116// AWDEN enumerated values
117pub const CR1_AWDEN_DISABLED: u32 = 0 << 23;
118pub const CR1_AWDEN_ENABLED: u32 = 1 << 23;
119
120pub const CR1_JAWDEN_POS: u32 = 22;
121pub const CR1_JAWDEN_WIDTH: u32 = 1;
122pub const CR1_JAWDEN_MASK: u32 = 0x1 << 22;
123// JAWDEN enumerated values
124pub const CR1_JAWDEN_DISABLED: u32 = 0 << 22;
125pub const CR1_JAWDEN_ENABLED: u32 = 1 << 22;
126
127pub const CR1_DISCNUM_POS: u32 = 13;
128pub const CR1_DISCNUM_WIDTH: u32 = 3;
129pub const CR1_DISCNUM_MASK: u32 = 0x7 << 13;
130
131pub const CR1_JDISCEN_POS: u32 = 12;
132pub const CR1_JDISCEN_WIDTH: u32 = 1;
133pub const CR1_JDISCEN_MASK: u32 = 0x1 << 12;
134// JDISCEN enumerated values
135pub const CR1_JDISCEN_DISABLED: u32 = 0 << 12;
136pub const CR1_JDISCEN_ENABLED: u32 = 1 << 12;
137
138pub const CR1_DISCEN_POS: u32 = 11;
139pub const CR1_DISCEN_WIDTH: u32 = 1;
140pub const CR1_DISCEN_MASK: u32 = 0x1 << 11;
141// DISCEN enumerated values
142pub const CR1_DISCEN_DISABLED: u32 = 0 << 11;
143pub const CR1_DISCEN_ENABLED: u32 = 1 << 11;
144
145pub const CR1_JAUTO_POS: u32 = 10;
146pub const CR1_JAUTO_WIDTH: u32 = 1;
147pub const CR1_JAUTO_MASK: u32 = 0x1 << 10;
148// JAUTO enumerated values
149pub const CR1_JAUTO_DISABLED: u32 = 0 << 10;
150pub const CR1_JAUTO_ENABLED: u32 = 1 << 10;
151
152pub const CR1_AWDSGL_POS: u32 = 9;
153pub const CR1_AWDSGL_WIDTH: u32 = 1;
154pub const CR1_AWDSGL_MASK: u32 = 0x1 << 9;
155// AWDSGL enumerated values
156pub const CR1_AWDSGL_ALLCHANNELS: u32 = 0 << 9;
157pub const CR1_AWDSGL_SINGLECHANNEL: u32 = 1 << 9;
158
159pub const CR1_SCAN_POS: u32 = 8;
160pub const CR1_SCAN_WIDTH: u32 = 1;
161pub const CR1_SCAN_MASK: u32 = 0x1 << 8;
162// SCAN enumerated values
163pub const CR1_SCAN_DISABLED: u32 = 0 << 8;
164pub const CR1_SCAN_ENABLED: u32 = 1 << 8;
165
166pub const CR1_JEOCIE_POS: u32 = 7;
167pub const CR1_JEOCIE_WIDTH: u32 = 1;
168pub const CR1_JEOCIE_MASK: u32 = 0x1 << 7;
169// JEOCIE enumerated values
170pub const CR1_JEOCIE_DISABLED: u32 = 0 << 7;
171pub const CR1_JEOCIE_ENABLED: u32 = 1 << 7;
172
173pub const CR1_AWDIE_POS: u32 = 6;
174pub const CR1_AWDIE_WIDTH: u32 = 1;
175pub const CR1_AWDIE_MASK: u32 = 0x1 << 6;
176// AWDIE enumerated values
177pub const CR1_AWDIE_DISABLED: u32 = 0 << 6;
178pub const CR1_AWDIE_ENABLED: u32 = 1 << 6;
179
180pub const CR1_EOCIE_POS: u32 = 5;
181pub const CR1_EOCIE_WIDTH: u32 = 1;
182pub const CR1_EOCIE_MASK: u32 = 0x1 << 5;
183// EOCIE enumerated values
184pub const CR1_EOCIE_DISABLED: u32 = 0 << 5;
185pub const CR1_EOCIE_ENABLED: u32 = 1 << 5;
186
187pub const CR1_AWDCH_POS: u32 = 0;
188pub const CR1_AWDCH_WIDTH: u32 = 5;
189pub const CR1_AWDCH_MASK: u32 = 0x1F << 0;
190
191// CR2 register fields
192pub const CR2_SWSTART_POS: u32 = 30;
193pub const CR2_SWSTART_WIDTH: u32 = 1;
194pub const CR2_SWSTART_MASK: u32 = 0x1 << 30;
195// SWSTART enumerated values
196pub const CR2_SWSTART_START: u32 = 1 << 30;
197
198pub const CR2_EXTEN_POS: u32 = 28;
199pub const CR2_EXTEN_WIDTH: u32 = 2;
200pub const CR2_EXTEN_MASK: u32 = 0x3 << 28;
201// EXTEN enumerated values
202pub const CR2_EXTEN_DISABLED: u32 = 0 << 28;
203pub const CR2_EXTEN_RISINGEDGE: u32 = 1 << 28;
204pub const CR2_EXTEN_FALLINGEDGE: u32 = 2 << 28;
205pub const CR2_EXTEN_BOTHEDGES: u32 = 3 << 28;
206
207pub const CR2_EXTSEL_POS: u32 = 24;
208pub const CR2_EXTSEL_WIDTH: u32 = 4;
209pub const CR2_EXTSEL_MASK: u32 = 0xF << 24;
210// EXTSEL enumerated values
211pub const CR2_EXTSEL_TIM1CC1: u32 = 0 << 24;
212pub const CR2_EXTSEL_TIM1CC2: u32 = 1 << 24;
213pub const CR2_EXTSEL_TIM1CC3: u32 = 2 << 24;
214pub const CR2_EXTSEL_TIM2CC2: u32 = 3 << 24;
215pub const CR2_EXTSEL_TIM2CC3: u32 = 4 << 24;
216pub const CR2_EXTSEL_TIM2CC4: u32 = 5 << 24;
217pub const CR2_EXTSEL_TIM2TRGO: u32 = 6 << 24;
218
219pub const CR2_JSWSTART_POS: u32 = 22;
220pub const CR2_JSWSTART_WIDTH: u32 = 1;
221pub const CR2_JSWSTART_MASK: u32 = 0x1 << 22;
222// JSWSTART enumerated values
223pub const CR2_JSWSTART_START: u32 = 1 << 22;
224
225pub const CR2_JEXTEN_POS: u32 = 20;
226pub const CR2_JEXTEN_WIDTH: u32 = 2;
227pub const CR2_JEXTEN_MASK: u32 = 0x3 << 20;
228// JEXTEN enumerated values
229pub const CR2_JEXTEN_DISABLED: u32 = 0 << 20;
230pub const CR2_JEXTEN_RISINGEDGE: u32 = 1 << 20;
231pub const CR2_JEXTEN_FALLINGEDGE: u32 = 2 << 20;
232pub const CR2_JEXTEN_BOTHEDGES: u32 = 3 << 20;
233
234pub const CR2_JEXTSEL_POS: u32 = 16;
235pub const CR2_JEXTSEL_WIDTH: u32 = 4;
236pub const CR2_JEXTSEL_MASK: u32 = 0xF << 16;
237// JEXTSEL enumerated values
238pub const CR2_JEXTSEL_TIM1TRGO: u32 = 0 << 16;
239pub const CR2_JEXTSEL_TIM1CC4: u32 = 1 << 16;
240pub const CR2_JEXTSEL_TIM2TRGO: u32 = 2 << 16;
241pub const CR2_JEXTSEL_TIM2CC1: u32 = 3 << 16;
242pub const CR2_JEXTSEL_TIM3CC4: u32 = 4 << 16;
243pub const CR2_JEXTSEL_TIM4TRGO: u32 = 5 << 16;
244pub const CR2_JEXTSEL_TIM8CC4: u32 = 7 << 16;
245pub const CR2_JEXTSEL_TIM1TRGO2: u32 = 8 << 16;
246pub const CR2_JEXTSEL_TIM8TRGO: u32 = 9 << 16;
247pub const CR2_JEXTSEL_TIM8TRGO2: u32 = 10 << 16;
248pub const CR2_JEXTSEL_TIM3CC3: u32 = 11 << 16;
249pub const CR2_JEXTSEL_TIM5TRGO: u32 = 12 << 16;
250pub const CR2_JEXTSEL_TIM3CC1: u32 = 13 << 16;
251pub const CR2_JEXTSEL_TIM6TRGO: u32 = 14 << 16;
252
253pub const CR2_ALIGN_POS: u32 = 11;
254pub const CR2_ALIGN_WIDTH: u32 = 1;
255pub const CR2_ALIGN_MASK: u32 = 0x1 << 11;
256// ALIGN enumerated values
257pub const CR2_ALIGN_RIGHT: u32 = 0 << 11;
258pub const CR2_ALIGN_LEFT: u32 = 1 << 11;
259
260pub const CR2_EOCS_POS: u32 = 10;
261pub const CR2_EOCS_WIDTH: u32 = 1;
262pub const CR2_EOCS_MASK: u32 = 0x1 << 10;
263// EOCS enumerated values
264pub const CR2_EOCS_EACHSEQUENCE: u32 = 0 << 10;
265pub const CR2_EOCS_EACHCONVERSION: u32 = 1 << 10;
266
267pub const CR2_DDS_POS: u32 = 9;
268pub const CR2_DDS_WIDTH: u32 = 1;
269pub const CR2_DDS_MASK: u32 = 0x1 << 9;
270// DDS enumerated values
271pub const CR2_DDS_SINGLE: u32 = 0 << 9;
272pub const CR2_DDS_CONTINUOUS: u32 = 1 << 9;
273
274pub const CR2_DMA_POS: u32 = 8;
275pub const CR2_DMA_WIDTH: u32 = 1;
276pub const CR2_DMA_MASK: u32 = 0x1 << 8;
277// DMA enumerated values
278pub const CR2_DMA_DISABLED: u32 = 0 << 8;
279pub const CR2_DMA_ENABLED: u32 = 1 << 8;
280
281pub const CR2_CONT_POS: u32 = 1;
282pub const CR2_CONT_WIDTH: u32 = 1;
283pub const CR2_CONT_MASK: u32 = 0x1 << 1;
284// CONT enumerated values
285pub const CR2_CONT_SINGLE: u32 = 0 << 1;
286pub const CR2_CONT_CONTINUOUS: u32 = 1 << 1;
287
288pub const CR2_ADON_POS: u32 = 0;
289pub const CR2_ADON_WIDTH: u32 = 1;
290pub const CR2_ADON_MASK: u32 = 0x1 << 0;
291// ADON enumerated values
292pub const CR2_ADON_DISABLED: u32 = 0 << 0;
293pub const CR2_ADON_ENABLED: u32 = 1 << 0;
294
295// SMPR1 register fields
296pub const SMPR1_SMP18_POS: u32 = 24;
297pub const SMPR1_SMP18_WIDTH: u32 = 3;
298pub const SMPR1_SMP18_MASK: u32 = 0x7 << 24;
299
300pub const SMPR1_SMP17_POS: u32 = 21;
301pub const SMPR1_SMP17_WIDTH: u32 = 3;
302pub const SMPR1_SMP17_MASK: u32 = 0x7 << 21;
303
304pub const SMPR1_SMP16_POS: u32 = 18;
305pub const SMPR1_SMP16_WIDTH: u32 = 3;
306pub const SMPR1_SMP16_MASK: u32 = 0x7 << 18;
307
308pub const SMPR1_SMP15_POS: u32 = 15;
309pub const SMPR1_SMP15_WIDTH: u32 = 3;
310pub const SMPR1_SMP15_MASK: u32 = 0x7 << 15;
311
312pub const SMPR1_SMP14_POS: u32 = 12;
313pub const SMPR1_SMP14_WIDTH: u32 = 3;
314pub const SMPR1_SMP14_MASK: u32 = 0x7 << 12;
315
316pub const SMPR1_SMP13_POS: u32 = 9;
317pub const SMPR1_SMP13_WIDTH: u32 = 3;
318pub const SMPR1_SMP13_MASK: u32 = 0x7 << 9;
319
320pub const SMPR1_SMP12_POS: u32 = 6;
321pub const SMPR1_SMP12_WIDTH: u32 = 3;
322pub const SMPR1_SMP12_MASK: u32 = 0x7 << 6;
323
324pub const SMPR1_SMP11_POS: u32 = 3;
325pub const SMPR1_SMP11_WIDTH: u32 = 3;
326pub const SMPR1_SMP11_MASK: u32 = 0x7 << 3;
327
328pub const SMPR1_SMP10_POS: u32 = 0;
329pub const SMPR1_SMP10_WIDTH: u32 = 3;
330pub const SMPR1_SMP10_MASK: u32 = 0x7 << 0;
331// SMP10 enumerated values
332pub const SMPR1_SMP10_CYCLES3: u32 = 0 << 0;
333pub const SMPR1_SMP10_CYCLES15: u32 = 1 << 0;
334pub const SMPR1_SMP10_CYCLES28: u32 = 2 << 0;
335pub const SMPR1_SMP10_CYCLES56: u32 = 3 << 0;
336pub const SMPR1_SMP10_CYCLES84: u32 = 4 << 0;
337pub const SMPR1_SMP10_CYCLES112: u32 = 5 << 0;
338pub const SMPR1_SMP10_CYCLES144: u32 = 6 << 0;
339pub const SMPR1_SMP10_CYCLES480: u32 = 7 << 0;
340
341// SMPR2 register fields
342pub const SMPR2_SMP9_POS: u32 = 27;
343pub const SMPR2_SMP9_WIDTH: u32 = 3;
344pub const SMPR2_SMP9_MASK: u32 = 0x7 << 27;
345
346pub const SMPR2_SMP8_POS: u32 = 24;
347pub const SMPR2_SMP8_WIDTH: u32 = 3;
348pub const SMPR2_SMP8_MASK: u32 = 0x7 << 24;
349
350pub const SMPR2_SMP7_POS: u32 = 21;
351pub const SMPR2_SMP7_WIDTH: u32 = 3;
352pub const SMPR2_SMP7_MASK: u32 = 0x7 << 21;
353
354pub const SMPR2_SMP6_POS: u32 = 18;
355pub const SMPR2_SMP6_WIDTH: u32 = 3;
356pub const SMPR2_SMP6_MASK: u32 = 0x7 << 18;
357
358pub const SMPR2_SMP5_POS: u32 = 15;
359pub const SMPR2_SMP5_WIDTH: u32 = 3;
360pub const SMPR2_SMP5_MASK: u32 = 0x7 << 15;
361
362pub const SMPR2_SMP4_POS: u32 = 12;
363pub const SMPR2_SMP4_WIDTH: u32 = 3;
364pub const SMPR2_SMP4_MASK: u32 = 0x7 << 12;
365
366pub const SMPR2_SMP3_POS: u32 = 9;
367pub const SMPR2_SMP3_WIDTH: u32 = 3;
368pub const SMPR2_SMP3_MASK: u32 = 0x7 << 9;
369
370pub const SMPR2_SMP2_POS: u32 = 6;
371pub const SMPR2_SMP2_WIDTH: u32 = 3;
372pub const SMPR2_SMP2_MASK: u32 = 0x7 << 6;
373
374pub const SMPR2_SMP1_POS: u32 = 3;
375pub const SMPR2_SMP1_WIDTH: u32 = 3;
376pub const SMPR2_SMP1_MASK: u32 = 0x7 << 3;
377
378pub const SMPR2_SMP0_POS: u32 = 0;
379pub const SMPR2_SMP0_WIDTH: u32 = 3;
380pub const SMPR2_SMP0_MASK: u32 = 0x7 << 0;
381// SMP0 enumerated values
382pub const SMPR2_SMP0_CYCLES3: u32 = 0 << 0;
383pub const SMPR2_SMP0_CYCLES15: u32 = 1 << 0;
384pub const SMPR2_SMP0_CYCLES28: u32 = 2 << 0;
385pub const SMPR2_SMP0_CYCLES56: u32 = 3 << 0;
386pub const SMPR2_SMP0_CYCLES84: u32 = 4 << 0;
387pub const SMPR2_SMP0_CYCLES112: u32 = 5 << 0;
388pub const SMPR2_SMP0_CYCLES144: u32 = 6 << 0;
389pub const SMPR2_SMP0_CYCLES480: u32 = 7 << 0;
390
391// JOFR register fields (injected channel data offset registers)
392pub const JOFR1_JOFFSET_POS: u32 = 0;
393pub const JOFR1_JOFFSET_WIDTH: u32 = 12;
394pub const JOFR1_JOFFSET_MASK: u32 = 0xFFF << 0;
395
396pub const JOFR2_JOFFSET_POS: u32 = 0;
397pub const JOFR2_JOFFSET_WIDTH: u32 = 12;
398pub const JOFR2_JOFFSET_MASK: u32 = 0xFFF << 0;
399
400pub const JOFR3_JOFFSET_POS: u32 = 0;
401pub const JOFR3_JOFFSET_WIDTH: u32 = 12;
402pub const JOFR3_JOFFSET_MASK: u32 = 0xFFF << 0;
403
404pub const JOFR4_JOFFSET_POS: u32 = 0;
405pub const JOFR4_JOFFSET_WIDTH: u32 = 12;
406pub const JOFR4_JOFFSET_MASK: u32 = 0xFFF << 0;
407
408// HTR register fields
409pub const HTR_HT_POS: u32 = 0;
410pub const HTR_HT_WIDTH: u32 = 12;
411pub const HTR_HT_MASK: u32 = 0xFFF << 0;
412
413// LTR register fields
414pub const LTR_LT_POS: u32 = 0;
415pub const LTR_LT_WIDTH: u32 = 12;
416pub const LTR_LT_MASK: u32 = 0xFFF << 0;
417
418// SQR1 register fields
419pub const SQR1_L_POS: u32 = 20;
420pub const SQR1_L_WIDTH: u32 = 4;
421pub const SQR1_L_MASK: u32 = 0xF << 20;
422
423pub const SQR1_SQ16_POS: u32 = 15;
424pub const SQR1_SQ16_WIDTH: u32 = 5;
425pub const SQR1_SQ16_MASK: u32 = 0x1F << 15;
426
427pub const SQR1_SQ15_POS: u32 = 10;
428pub const SQR1_SQ15_WIDTH: u32 = 5;
429pub const SQR1_SQ15_MASK: u32 = 0x1F << 10;
430
431pub const SQR1_SQ14_POS: u32 = 5;
432pub const SQR1_SQ14_WIDTH: u32 = 5;
433pub const SQR1_SQ14_MASK: u32 = 0x1F << 5;
434
435pub const SQR1_SQ13_POS: u32 = 0;
436pub const SQR1_SQ13_WIDTH: u32 = 5;
437pub const SQR1_SQ13_MASK: u32 = 0x1F << 0;
438
439// SQR2 register fields
440pub const SQR2_SQ12_POS: u32 = 25;
441pub const SQR2_SQ12_WIDTH: u32 = 5;
442pub const SQR2_SQ12_MASK: u32 = 0x1F << 25;
443
444pub const SQR2_SQ11_POS: u32 = 20;
445pub const SQR2_SQ11_WIDTH: u32 = 5;
446pub const SQR2_SQ11_MASK: u32 = 0x1F << 20;
447
448pub const SQR2_SQ10_POS: u32 = 15;
449pub const SQR2_SQ10_WIDTH: u32 = 5;
450pub const SQR2_SQ10_MASK: u32 = 0x1F << 15;
451
452pub const SQR2_SQ9_POS: u32 = 10;
453pub const SQR2_SQ9_WIDTH: u32 = 5;
454pub const SQR2_SQ9_MASK: u32 = 0x1F << 10;
455
456pub const SQR2_SQ8_POS: u32 = 5;
457pub const SQR2_SQ8_WIDTH: u32 = 5;
458pub const SQR2_SQ8_MASK: u32 = 0x1F << 5;
459
460pub const SQR2_SQ7_POS: u32 = 0;
461pub const SQR2_SQ7_WIDTH: u32 = 5;
462pub const SQR2_SQ7_MASK: u32 = 0x1F << 0;
463
464// SQR3 register fields
465pub const SQR3_SQ6_POS: u32 = 25;
466pub const SQR3_SQ6_WIDTH: u32 = 5;
467pub const SQR3_SQ6_MASK: u32 = 0x1F << 25;
468
469pub const SQR3_SQ5_POS: u32 = 20;
470pub const SQR3_SQ5_WIDTH: u32 = 5;
471pub const SQR3_SQ5_MASK: u32 = 0x1F << 20;
472
473pub const SQR3_SQ4_POS: u32 = 15;
474pub const SQR3_SQ4_WIDTH: u32 = 5;
475pub const SQR3_SQ4_MASK: u32 = 0x1F << 15;
476
477pub const SQR3_SQ3_POS: u32 = 10;
478pub const SQR3_SQ3_WIDTH: u32 = 5;
479pub const SQR3_SQ3_MASK: u32 = 0x1F << 10;
480
481pub const SQR3_SQ2_POS: u32 = 5;
482pub const SQR3_SQ2_WIDTH: u32 = 5;
483pub const SQR3_SQ2_MASK: u32 = 0x1F << 5;
484
485pub const SQR3_SQ1_POS: u32 = 0;
486pub const SQR3_SQ1_WIDTH: u32 = 5;
487pub const SQR3_SQ1_MASK: u32 = 0x1F << 0;
488
489// JSQR register fields
490pub const JSQR_JL_POS: u32 = 20;
491pub const JSQR_JL_WIDTH: u32 = 2;
492pub const JSQR_JL_MASK: u32 = 0x3 << 20;
493
494pub const JSQR_JSQ4_POS: u32 = 15;
495pub const JSQR_JSQ4_WIDTH: u32 = 5;
496pub const JSQR_JSQ4_MASK: u32 = 0x1F << 15;
497
498pub const JSQR_JSQ3_POS: u32 = 10;
499pub const JSQR_JSQ3_WIDTH: u32 = 5;
500pub const JSQR_JSQ3_MASK: u32 = 0x1F << 10;
501
502pub const JSQR_JSQ2_POS: u32 = 5;
503pub const JSQR_JSQ2_WIDTH: u32 = 5;
504pub const JSQR_JSQ2_MASK: u32 = 0x1F << 5;
505
506pub const JSQR_JSQ1_POS: u32 = 0;
507pub const JSQR_JSQ1_WIDTH: u32 = 5;
508pub const JSQR_JSQ1_MASK: u32 = 0x1F << 0;
509
510// JDR register fields (injected data registers)
511pub const JDR1_JDATA_POS: u32 = 0;
512pub const JDR1_JDATA_WIDTH: u32 = 16;
513pub const JDR1_JDATA_MASK: u32 = 0xFFFF << 0;
514
515pub const JDR2_JDATA_POS: u32 = 0;
516pub const JDR2_JDATA_WIDTH: u32 = 16;
517pub const JDR2_JDATA_MASK: u32 = 0xFFFF << 0;
518
519pub const JDR3_JDATA_POS: u32 = 0;
520pub const JDR3_JDATA_WIDTH: u32 = 16;
521pub const JDR3_JDATA_MASK: u32 = 0xFFFF << 0;
522
523pub const JDR4_JDATA_POS: u32 = 0;
524pub const JDR4_JDATA_WIDTH: u32 = 16;
525pub const JDR4_JDATA_MASK: u32 = 0xFFFF << 0;
526
527// DR register fields
528pub const DR_DATA_POS: u32 = 0;
529pub const DR_DATA_WIDTH: u32 = 16;
530pub const DR_DATA_MASK: u32 = 0xFFFF << 0;
531
532// ADC Resolution enumeration
533#[derive(Copy, Clone, Debug, PartialEq)]
534pub enum AdcResolution {
535    Bits12 = 0,
536    Bits10 = 1,
537    Bits8 = 2,
538    Bits6 = 3,
539}
540
541// ADC Sample Time enumeration
542#[derive(Copy, Clone, Debug, PartialEq)]
543pub enum AdcSampleTime {
544    Cycles3 = 0,
545    Cycles15 = 1,
546    Cycles28 = 2,
547    Cycles56 = 3,
548    Cycles84 = 4,
549    Cycles112 = 5,
550    Cycles144 = 6,
551    Cycles480 = 7,
552}
553
554// Helper functions for ADC
555impl RegisterBlock {
556    /// Enable ADC
557    pub fn enable(&mut self) {
558        self.cr2 |= CR2_ADON_MASK;
559    }
560
561    /// Disable ADC
562    pub fn disable(&mut self) {
563        self.cr2 &= !CR2_ADON_MASK;
564    }
565
566    /// Set ADC resolution
567    pub fn set_resolution(&mut self, resolution: AdcResolution) {
568        self.cr1 = (self.cr1 & !CR1_RES_MASK) | ((resolution as u32) << CR1_RES_POS);
569    }
570
571    /// Enable continuous conversion mode
572    pub fn enable_continuous(&mut self) {
573        self.cr2 |= CR2_CONT_MASK;
574    }
575
576    /// Disable continuous conversion mode
577    pub fn disable_continuous(&mut self) {
578        self.cr2 &= !CR2_CONT_MASK;
579    }
580
581    /// Start software conversion
582    pub fn start_conversion(&mut self) {
583        self.cr2 |= CR2_SWSTART_MASK;
584    }
585
586    /// Check if conversion is complete
587    pub fn is_conversion_complete(&self) -> bool {
588        (self.sr & SR_EOC_MASK) != 0
589    }
590
591    /// Clear end of conversion flag
592    pub fn clear_eoc_flag(&mut self) {
593        self.sr &= !SR_EOC_MASK;
594    }
595
596    /// Read conversion result
597    pub fn read_data(&self) -> u16 {
598        self.dr as u16
599    }
600
601    /// Set sample time for channel (0-9)
602    pub fn set_sample_time_low(&mut self, channel: u8, sample_time: AdcSampleTime) {
603        if channel < 10 {
604            let shift = channel * 3;
605            let mask = 0x7 << shift;
606            self.smpr2 = (self.smpr2 & !mask) | ((sample_time as u32) << shift);
607        }
608    }
609
610    /// Set sample time for channel (10-18)
611    pub fn set_sample_time_high(&mut self, channel: u8, sample_time: AdcSampleTime) {
612        if channel >= 10 && channel < 19 {
613            let shift = (channel - 10) * 3;
614            let mask = 0x7 << shift;
615            self.smpr1 = (self.smpr1 & !mask) | ((sample_time as u32) << shift);
616        }
617    }
618
619    /// Set first regular sequence channel
620    pub fn set_regular_sequence_1(&mut self, channel: u8) {
621        self.sqr3 = (self.sqr3 & !0x1F) | (channel as u32 & 0x1F);
622    }
623
624    /// Set regular sequence length
625    pub fn set_regular_sequence_length(&mut self, length: u8) {
626        if length > 0 && length <= 16 {
627            let len = (length - 1) as u32;
628            self.sqr1 = (self.sqr1 & !0xF00000) | ((len & 0xF) << 20);
629        }
630    }
631
632    /// Perform single conversion on a channel
633    pub fn single_conversion(&mut self, channel: u8) -> u16 {
634        // Set channel as first in sequence
635        self.set_regular_sequence_1(channel);
636        self.set_regular_sequence_length(1);
637
638        // Start conversion
639        self.start_conversion();
640
641        // Wait for completion
642        while !self.is_conversion_complete() {}
643
644        // Read result
645        self.read_data()
646    }
647}
stm32_rust_template/mcu/stm32f407/adc.rs

stm32_rust_template/mcu/stm32f407/
adc.rs
