Structs§
Enums§
Constants§
- CR1_
BIDIMODE_ BIDIRECTIONAL - CR1_
BIDIMODE_ MASK - CR1_
BIDIMODE_ POS - CR1_
BIDIMODE_ UNIDIRECTIONAL - CR1_
BIDIMODE_ WIDTH - CR1_
BIDIOE_ MASK - CR1_
BIDIOE_ OUTPUTDISABLED - CR1_
BIDIOE_ OUTPUTENABLED - CR1_
BIDIOE_ POS - CR1_
BIDIOE_ WIDTH - CR1_
BR_ DIV2 - CR1_
BR_ DIV4 - CR1_
BR_ DIV8 - CR1_
BR_ DIV16 - CR1_
BR_ DIV32 - CR1_
BR_ DIV64 - CR1_
BR_ DIV128 - CR1_
BR_ DIV256 - CR1_
BR_ MASK - CR1_
BR_ POS - CR1_
BR_ WIDTH - CR1_
CPHA_ FIRSTEDGE - CR1_
CPHA_ MASK - CR1_
CPHA_ POS - CR1_
CPHA_ SECONDEDGE - CR1_
CPHA_ WIDTH - CR1_
CPOL_ IDLEHIGH - CR1_
CPOL_ IDLELOW - CR1_
CPOL_ MASK - CR1_
CPOL_ POS - CR1_
CPOL_ WIDTH - CR1_
CRCEN_ DISABLED - CR1_
CRCEN_ ENABLED - CR1_
CRCEN_ MASK - CR1_
CRCEN_ POS - CR1_
CRCEN_ WIDTH - CR1_
CRCNEXT_ CRC - CR1_
CRCNEXT_ MASK - CR1_
CRCNEXT_ POS - CR1_
CRCNEXT_ TXBUFFER - CR1_
CRCNEXT_ WIDTH - CR1_
DFF_ EIGHTBIT - CR1_
DFF_ MASK - CR1_
DFF_ POS - CR1_
DFF_ SIXTEENBIT - CR1_
DFF_ WIDTH - CR1_
LSBFIRST_ LSBFIRST - CR1_
LSBFIRST_ MASK - CR1_
LSBFIRST_ MSBFIRST - CR1_
LSBFIRST_ POS - CR1_
LSBFIRST_ WIDTH - CR1_
MSTR_ MASK - CR1_
MSTR_ MASTER - CR1_
MSTR_ POS - CR1_
MSTR_ SLAVE - CR1_
MSTR_ WIDTH - CR1_
RXONLY_ FULLDUPLEX - CR1_
RXONLY_ MASK - CR1_
RXONLY_ OUTPUTDISABLED - CR1_
RXONLY_ POS - CR1_
RXONLY_ WIDTH - CR1_
SPE_ DISABLED - CR1_
SPE_ ENABLED - CR1_
SPE_ MASK - CR1_
SPE_ POS - CR1_
SPE_ WIDTH - CR1_
SSI_ MASK - CR1_
SSI_ POS - CR1_
SSI_ SLAVENOTSELECTED - CR1_
SSI_ SLAVESELECTED - CR1_
SSI_ WIDTH - CR1_
SSM_ DISABLED - CR1_
SSM_ ENABLED - CR1_
SSM_ MASK - CR1_
SSM_ POS - CR1_
SSM_ WIDTH - CR2_
ERRIE_ MASK - CR2_
ERRIE_ MASKED - CR2_
ERRIE_ NOTMASKED - CR2_
ERRIE_ POS - CR2_
ERRIE_ WIDTH - CR2_
FRF_ MASK - CR2_
FRF_ MOTOROLA - CR2_
FRF_ POS - CR2_
FRF_ TI - CR2_
FRF_ WIDTH - CR2_
RXDMAEN_ DISABLED - CR2_
RXDMAEN_ ENABLED - CR2_
RXDMAEN_ MASK - CR2_
RXDMAEN_ POS - CR2_
RXDMAEN_ WIDTH - CR2_
RXNEIE_ MASK - CR2_
RXNEIE_ MASKED - CR2_
RXNEIE_ NOTMASKED - CR2_
RXNEIE_ POS - CR2_
RXNEIE_ WIDTH - CR2_
SSOE_ DISABLED - CR2_
SSOE_ ENABLED - CR2_
SSOE_ MASK - CR2_
SSOE_ POS - CR2_
SSOE_ WIDTH - CR2_
TXDMAEN_ DISABLED - CR2_
TXDMAEN_ ENABLED - CR2_
TXDMAEN_ MASK - CR2_
TXDMAEN_ POS - CR2_
TXDMAEN_ WIDTH - CR2_
TXEIE_ MASK - CR2_
TXEIE_ MASKED - CR2_
TXEIE_ NOTMASKED - CR2_
TXEIE_ POS - CR2_
TXEIE_ WIDTH - CRCPR_
CRCPOLY_ MASK - CRCPR_
CRCPOLY_ POS - CRCPR_
CRCPOLY_ WIDTH - DR_
DR_ MASK - DR_
DR_ POS - DR_
DR_ WIDTH - I2SCFGR_
CHLEN_ MASK - I2SCFGR_
CHLEN_ POS - I2SCFGR_
CHLEN_ SIXTEENBIT - I2SCFGR_
CHLEN_ THIRTYTWOBIT - I2SCFGR_
CHLEN_ WIDTH - I2SCFGR_
CKPOL_ IDLEHIGH - I2SCFGR_
CKPOL_ IDLELOW - I2SCFGR_
CKPOL_ MASK - I2SCFGR_
CKPOL_ POS - I2SCFGR_
CKPOL_ WIDTH - I2SCFGR_
DATLEN_ MASK - I2SCFGR_
DATLEN_ POS - I2SCFGR_
DATLEN_ SIXTEENBIT - I2SCFGR_
DATLEN_ THIRTYTWOBIT - I2SCFGR_
DATLEN_ TWENTYFOURBIT - I2SCFGR_
DATLEN_ WIDTH - I2SCFGR_
I2SCFG_ MASK - I2SCFGR_
I2SCFG_ MASTERRX - I2SCFGR_
I2SCFG_ MASTERTX - I2SCFGR_
I2SCFG_ POS - I2SCFGR_
I2SCFG_ SLAVERX - I2SCFGR_
I2SCFG_ SLAVETX - I2SCFGR_
I2SCFG_ WIDTH - I2SCFGR_
I2SE_ DISABLED - I2SCFGR_
I2SE_ ENABLED - I2SCFGR_
I2SE_ MASK - I2SCFGR_
I2SE_ POS - I2SCFGR_
I2SE_ WIDTH - I2SCFGR_
I2SMOD_ I2SMODE - I2SCFGR_
I2SMOD_ MASK - I2SCFGR_
I2SMOD_ POS - I2SCFGR_
I2SMOD_ SPIMODE - I2SCFGR_
I2SMOD_ WIDTH - I2SCFGR_
I2SSTD_ LSB - I2SCFGR_
I2SSTD_ MASK - I2SCFGR_
I2SSTD_ MSB - I2SCFGR_
I2SSTD_ PCM - I2SCFGR_
I2SSTD_ PHILIPS - I2SCFGR_
I2SSTD_ POS - I2SCFGR_
I2SSTD_ WIDTH - I2SCFGR_
PCMSYNC_ LONG - I2SCFGR_
PCMSYNC_ MASK - I2SCFGR_
PCMSYNC_ POS - I2SCFGR_
PCMSYNC_ SHORT - I2SCFGR_
PCMSYNC_ WIDTH - I2SPR_
I2SDIV_ MASK - I2SPR_
I2SDIV_ POS - I2SPR_
I2SDIV_ WIDTH - I2SPR_
MCKOE_ DISABLED - I2SPR_
MCKOE_ ENABLED - I2SPR_
MCKOE_ MASK - I2SPR_
MCKOE_ POS - I2SPR_
MCKOE_ WIDTH - I2SPR_
ODD_ EVEN - I2SPR_
ODD_ MASK - I2SPR_
ODD_ ODD - I2SPR_
ODD_ POS - I2SPR_
ODD_ WIDTH - RXCRCR_
RXCRC_ MASK - RXCRCR_
RXCRC_ POS - RXCRCR_
RXCRC_ WIDTH - SR_
BSY_ BUSY - SR_
BSY_ MASK - SR_
BSY_ NOTBUSY - SR_
BSY_ POS - SR_
BSY_ WIDTH - SR_
CHSIDE_ LEFT - SR_
CHSIDE_ MASK - SR_
CHSIDE_ POS - SR_
CHSIDE_ RIGHT - SR_
CHSIDE_ WIDTH - SR_
CRCERR_ MASK - SR_
CRCERR_ MATCH - SR_
CRCERR_ NOMATCH - SR_
CRCERR_ POS - SR_
CRCERR_ WIDTH - SR_
FRE_ ERROR - SR_
FRE_ MASK - SR_
FRE_ NOERROR - SR_
FRE_ POS - SR_
FRE_ WIDTH - SR_
MODF_ FAULT - SR_
MODF_ MASK - SR_
MODF_ NOFAULT - SR_
MODF_ POS - SR_
MODF_ WIDTH - SR_
OVR_ MASK - SR_
OVR_ NOOVERRUN - SR_
OVR_ OVERRUN - SR_
OVR_ POS - SR_
OVR_ WIDTH - SR_
RXNE_ EMPTY - SR_
RXNE_ MASK - SR_
RXNE_ NOTEMPTY - SR_
RXNE_ POS - SR_
RXNE_ WIDTH - SR_
TXE_ EMPTY - SR_
TXE_ MASK - SR_
TXE_ NOTEMPTY - SR_
TXE_ POS - SR_
TXE_ WIDTH - SR_
UDR_ MASK - SR_
UDR_ NOUNDERRUN - SR_
UDR_ POS - SR_
UDR_ UNDERRUN - SR_
UDR_ WIDTH - TXCRCR_
TXCRC_ MASK - TXCRCR_
TXCRC_ POS - TXCRCR_
TXCRC_ WIDTH