stm32_rust_template/mcu/stm32g030/
mod.rs

1// STM32G030 MCU-specific definitions
2
3// Base addresses
4pub const TIM2_BASEADDR: u32 = 0x40000000;
5pub const TIM3_BASEADDR: u32 = 0x40000400;
6pub const TIM14_BASEADDR: u32 = 0x40002000;
7pub const RTC_BASEADDR: u32 = 0x40002800;
8pub const WWDG_BASEADDR: u32 = 0x40002C00;
9pub const IWDG_BASEADDR: u32 = 0x40003000;
10pub const SPI2_BASEADDR: u32 = 0x40003800;
11pub const USART2_BASEADDR: u32 = 0x40004400;
12pub const I2C1_BASEADDR: u32 = 0x40005400;
13pub const I2C2_BASEADDR: u32 = 0x40005800;
14pub const PWR_BASEADDR: u32 = 0x40007000;
15pub const SYSCFG_BASEADDR: u32 = 0x40010000;
16pub const ADC_BASEADDR: u32 = 0x40012400;
17pub const TIM1_BASEADDR: u32 = 0x40012C00;
18pub const SPI1_BASEADDR: u32 = 0x40013000;
19pub const USART1_BASEADDR: u32 = 0x40013800;
20pub const TIM16_BASEADDR: u32 = 0x40014400;
21pub const TIM17_BASEADDR: u32 = 0x40014800;
22pub const GPIOA_BASEADDR: u32 = 0x50000000;
23pub const GPIOB_BASEADDR: u32 = 0x50000400;
24pub const GPIOC_BASEADDR: u32 = 0x50000800;
25pub const GPIOD_BASEADDR: u32 = 0x50000C00;
26pub const GPIOF_BASEADDR: u32 = 0x50001400;
27pub const RCC_BASEADDR: u32 = 0x40021000;
28pub const EXTI_BASEADDR: u32 = 0x40021800;
29pub const FLASH_R_BASEADDR: u32 = 0x40022000;
30pub const CRC_BASEADDR: u32 = 0x40023000;
31pub const DMA_BASEADDR: u32 = 0x40020000;
32
33/*
34 * IRQ(Interrupt Request) Numbers of STM32G030xx MCU
35 */
36#[allow(non_camel_case_types)]
37#[repr(u8)]
38pub enum IRQn {
39    WWDG = 0,
40    RTC_TAMP = 2,
41    FLASH = 3,
42    RCC = 4,
43    EXTI0_1 = 5,
44    EXTI2_3 = 6,
45    EXTI4_15 = 7,
46    DMA1_Channel1 = 9,
47    DMA1_Channel2_3 = 10,
48    DMA1_Ch4_5_DMAMUX1_OVR = 11,
49    ADC = 12,
50    TIM1_BRK_UP_TRG_COM = 13,
51    TIM1_CC = 14,
52    TIM2 = 15,
53    TIM3 = 16,
54    TIM14 = 19,
55    TIM16 = 21,
56    TIM17 = 22,
57    I2C1 = 23,
58    I2C2 = 24,
59    SPI1 = 25,
60    SPI2 = 26,
61    USART1 = 27,
62    USART2 = 28,
63    LPTIM1 = 29,
64    LPTIM2 = 30,
65    TIM6_DAC_LPTIM1 = 31,
66    TIM7_LPTIM2 = 32,
67    LPUART1 = 33,
68}
69
70pub trait PeripheralAccess {
71    const BASE_ADDRESS: u32;
72    type RegisterBlock;
73
74    fn ptr() -> *const Self::RegisterBlock {
75        Self::BASE_ADDRESS as *const Self::RegisterBlock
76    }
77
78    fn ptr_mut() -> *mut Self::RegisterBlock {
79        Self::BASE_ADDRESS as *mut Self::RegisterBlock
80    }
81}
82
83// Include peripheral modules
84pub mod gpio;
85pub mod rcc;
86// Add other peripherals as needed
stm32_rust_template/mcu/stm32g030/mod.rs

stm32_rust_template/mcu/stm32g030/
mod.rs
