stm32_rust_template/mcu/stm32f411/
mod.rs

1// STM32F411 MCU-specific definitions
2
3// Base addresses
4pub const TIM2_BASEADDR: u32 = 0x40000000;
5pub const TIM3_BASEADDR: u32 = 0x40000400;
6pub const TIM4_BASEADDR: u32 = 0x40000800;
7pub const TIM5_BASEADDR: u32 = 0x40000C00;
8pub const RTC_BASEADDR: u32 = 0x40002800;
9pub const WWDG_BASEADDR: u32 = 0x40002C00;
10pub const IWDG_BASEADDR: u32 = 0x40003000;
11pub const SPI2_BASEADDR: u32 = 0x40003800;
12pub const SPI3_BASEADDR: u32 = 0x40003C00;
13pub const USART2_BASEADDR: u32 = 0x40004400;
14pub const I2C1_BASEADDR: u32 = 0x40005400;
15pub const I2C2_BASEADDR: u32 = 0x40005800;
16pub const I2C3_BASEADDR: u32 = 0x40005C00;
17pub const PWR_BASEADDR: u32 = 0x40007000;
18pub const TIM1_BASEADDR: u32 = 0x40010000;
19pub const USART1_BASEADDR: u32 = 0x40011000;
20pub const USART6_BASEADDR: u32 = 0x40011400;
21pub const ADC1_BASEADDR: u32 = 0x40012000;
22pub const ADC_COMMON_BASEADDR: u32 = 0x40012300;
23pub const SDIO_BASEADDR: u32 = 0x40012C00;
24pub const SPI1_BASEADDR: u32 = 0x40013000;
25pub const SPI4_BASEADDR: u32 = 0x40013400;
26pub const SYSCFG_BASEADDR: u32 = 0x40013800;
27pub const EXTI_BASEADDR: u32 = 0x40013C00;
28pub const TIM9_BASEADDR: u32 = 0x40014000;
29pub const TIM10_BASEADDR: u32 = 0x40014400;
30pub const TIM11_BASEADDR: u32 = 0x40014800;
31pub const SPI5_BASEADDR: u32 = 0x40015000;
32pub const GPIOA_BASEADDR: u32 = 0x40020000;
33pub const GPIOB_BASEADDR: u32 = 0x40020400;
34pub const GPIOC_BASEADDR: u32 = 0x40020800;
35pub const GPIOD_BASEADDR: u32 = 0x40020C00;
36pub const GPIOE_BASEADDR: u32 = 0x40021000;
37pub const GPIOH_BASEADDR: u32 = 0x40021C00;
38pub const CRC_BASEADDR: u32 = 0x40023000;
39pub const RCC_BASEADDR: u32 = 0x40023800;
40pub const FLASH_R_BASEADDR: u32 = 0x40023C00;
41pub const DMA1_BASEADDR: u32 = 0x40026000;
42pub const DMA2_BASEADDR: u32 = 0x40026400;
43pub const USB_OTG_FS_BASEADDR: u32 = 0x50000000;
44
45/*
46 * IRQ(Interrupt Request) Numbers of STM32F411xE MCU
47 */
48#[allow(non_camel_case_types)]
49#[repr(u8)]
50pub enum IRQn {
51    WWDG = 0,
52    PVD = 1,
53    TAMP_STAMP = 2,
54    RTC_WKUP = 3,
55    FLASH = 4,
56    RCC = 5,
57    EXTI0 = 6,
58    EXTI1 = 7,
59    EXTI2 = 8,
60    EXTI3 = 9,
61    EXTI4 = 10,
62    DMA1_Stream0 = 11,
63    DMA1_Stream1 = 12,
64    DMA1_Stream2 = 13,
65    DMA1_Stream3 = 14,
66    DMA1_Stream4 = 15,
67    DMA1_Stream5 = 16,
68    DMA1_Stream6 = 17,
69    ADC = 18,
70    // Reserved = 19,
71    // Reserved = 20,
72    // Reserved = 21,
73    // Reserved = 22,
74    EXTI9_5 = 23,
75    TIM1_BRK_TIM9 = 24,
76    TIM1_UP_TIM10 = 25,
77    TIM1_TRG_COM_TIM11 = 26,
78    TIM1_CC = 27,
79    TIM2 = 28,
80    TIM3 = 29,
81    TIM4 = 30,
82    I2C1_EV = 31,
83    I2C1_ER = 32,
84    I2C2_EV = 33,
85    I2C2_ER = 34,
86    SPI1 = 35,
87    SPI2 = 36,
88    USART1 = 37,
89    USART2 = 38,
90    // Reserved = 39,
91    EXTI15_10 = 40,
92    RTC_Alarm = 41,
93    OTG_FS_WKUP = 42,
94    // Reserved = 43,
95    // Reserved = 44,
96    // Reserved = 45,
97    // Reserved = 46,
98    DMA1_Stream7 = 47,
99    // Reserved = 48,
100    SDIO = 49,
101    TIM5 = 50,
102    SPI3 = 51,
103    // Reserved = 52,
104    // Reserved = 53,
105    // Reserved = 54,
106    // Reserved = 55,
107    DMA2_Stream0 = 56,
108    DMA2_Stream1 = 57,
109    DMA2_Stream2 = 58,
110    DMA2_Stream3 = 59,
111    DMA2_Stream4 = 60,
112    // Reserved = 61,
113    // Reserved = 62,
114    // Reserved = 63,
115    // Reserved = 64,
116    // Reserved = 65,
117    // Reserved = 66,
118    OTG_FS = 67,
119    DMA2_Stream5 = 68,
120    DMA2_Stream6 = 69,
121    DMA2_Stream7 = 70,
122    USART6 = 71,
123    I2C3_EV = 72,
124    I2C3_ER = 73,
125    // Reserved = 74,
126    // Reserved = 75,
127    // Reserved = 76,
128    // Reserved = 77,
129    // Reserved = 78,
130    // Reserved = 79,
131    // Reserved = 80,
132    FPU = 81,
133    // Reserved = 82,
134    // Reserved = 83,
135    SPI4 = 84,
136    SPI5 = 85,
137}
138
139pub trait PeripheralAccess {
140    const BASE_ADDRESS: u32;
141    type RegisterBlock;
142
143    fn ptr() -> *const Self::RegisterBlock {
144        Self::BASE_ADDRESS as *const Self::RegisterBlock
145    }
146
147    fn ptr_mut() -> *mut Self::RegisterBlock {
148        Self::BASE_ADDRESS as *mut Self::RegisterBlock
149    }
150}
151
152// Include peripheral modules
153pub mod gpio;
154pub mod rcc;
155// Add other peripherals as needed
stm32_rust_template/mcu/stm32f411/mod.rs

stm32_rust_template/mcu/stm32f411/
mod.rs
