stm32_rust_template/mcu/stm32f407/
usart.rs

1// USART peripheral definitions
2// Generated from STM32F407 SVD file
3
4use super::{PeripheralAccess, USART1_BASEADDR, USART2_BASEADDR, USART3_BASEADDR};
5
6// USART Register Block
7#[repr(C)]
8pub struct RegisterBlock {
9    pub sr: u32,   // RO: Status register
10    pub dr: u32,   // RW: Data register
11    pub brr: u32,  // RW: Baud rate register
12    pub cr1: u32,  // RW: Control register 1
13    pub cr2: u32,  // RW: Control register 2
14    pub cr3: u32,  // RW: Control register 3
15    pub gtpr: u32, // RW: Guard time and prescaler register
16}
17
18// USART peripheral instances
19pub struct USART1;
20pub struct USART2;
21pub struct USART3;
22
23impl PeripheralAccess for USART1 {
24    const BASE_ADDRESS: u32 = USART1_BASEADDR;
25    type RegisterBlock = RegisterBlock;
26}
27
28impl PeripheralAccess for USART2 {
29    const BASE_ADDRESS: u32 = USART2_BASEADDR;
30    type RegisterBlock = RegisterBlock;
31}
32
33impl PeripheralAccess for USART3 {
34    const BASE_ADDRESS: u32 = USART3_BASEADDR;
35    type RegisterBlock = RegisterBlock;
36}
37
38// USART Register Field Definitions
39
40// SR register fields
41pub const SR_CTS_POS: u32 = 9;
42pub const SR_CTS_WIDTH: u32 = 1;
43pub const SR_CTS_MASK: u32 = 0x1 << 9;
44
45pub const SR_LBD_POS: u32 = 8;
46pub const SR_LBD_WIDTH: u32 = 1;
47pub const SR_LBD_MASK: u32 = 0x1 << 8;
48
49pub const SR_TXE_POS: u32 = 7;
50pub const SR_TXE_WIDTH: u32 = 1;
51pub const SR_TXE_MASK: u32 = 0x1 << 7;
52
53pub const SR_TC_POS: u32 = 6;
54pub const SR_TC_WIDTH: u32 = 1;
55pub const SR_TC_MASK: u32 = 0x1 << 6;
56
57pub const SR_RXNE_POS: u32 = 5;
58pub const SR_RXNE_WIDTH: u32 = 1;
59pub const SR_RXNE_MASK: u32 = 0x1 << 5;
60
61pub const SR_IDLE_POS: u32 = 4;
62pub const SR_IDLE_WIDTH: u32 = 1;
63pub const SR_IDLE_MASK: u32 = 0x1 << 4;
64
65pub const SR_ORE_POS: u32 = 3;
66pub const SR_ORE_WIDTH: u32 = 1;
67pub const SR_ORE_MASK: u32 = 0x1 << 3;
68
69pub const SR_NF_POS: u32 = 2;
70pub const SR_NF_WIDTH: u32 = 1;
71pub const SR_NF_MASK: u32 = 0x1 << 2;
72
73pub const SR_FE_POS: u32 = 1;
74pub const SR_FE_WIDTH: u32 = 1;
75pub const SR_FE_MASK: u32 = 0x1 << 1;
76
77pub const SR_PE_POS: u32 = 0;
78pub const SR_PE_WIDTH: u32 = 1;
79pub const SR_PE_MASK: u32 = 0x1 << 0;
80
81// DR register fields
82pub const DR_DR_POS: u32 = 0;
83pub const DR_DR_WIDTH: u32 = 9;
84pub const DR_DR_MASK: u32 = 0x1FF << 0;
85
86// BRR register fields
87pub const BRR_DIV_MANTISSA_POS: u32 = 4;
88pub const BRR_DIV_MANTISSA_WIDTH: u32 = 12;
89pub const BRR_DIV_MANTISSA_MASK: u32 = 0xFFF << 4;
90
91pub const BRR_DIV_FRACTION_POS: u32 = 0;
92pub const BRR_DIV_FRACTION_WIDTH: u32 = 4;
93pub const BRR_DIV_FRACTION_MASK: u32 = 0xF << 0;
94
95// CR1 register fields
96pub const CR1_OVER8_POS: u32 = 15;
97pub const CR1_OVER8_WIDTH: u32 = 1;
98pub const CR1_OVER8_MASK: u32 = 0x1 << 15;
99// OVER8 enumerated values
100pub const CR1_OVER8_OVERSAMPLE16: u32 = 0 << 15;
101pub const CR1_OVER8_OVERSAMPLE8: u32 = 1 << 15;
102
103pub const CR1_UE_POS: u32 = 13;
104pub const CR1_UE_WIDTH: u32 = 1;
105pub const CR1_UE_MASK: u32 = 0x1 << 13;
106// UE enumerated values
107pub const CR1_UE_DISABLED: u32 = 0 << 13;
108pub const CR1_UE_ENABLED: u32 = 1 << 13;
109
110pub const CR1_M_POS: u32 = 12;
111pub const CR1_M_WIDTH: u32 = 1;
112pub const CR1_M_MASK: u32 = 0x1 << 12;
113// M enumerated values
114pub const CR1_M_M8: u32 = 0 << 12;
115pub const CR1_M_M9: u32 = 1 << 12;
116
117pub const CR1_WAKE_POS: u32 = 11;
118pub const CR1_WAKE_WIDTH: u32 = 1;
119pub const CR1_WAKE_MASK: u32 = 0x1 << 11;
120// WAKE enumerated values
121pub const CR1_WAKE_IDLELINE: u32 = 0 << 11;
122pub const CR1_WAKE_ADDRESSMARK: u32 = 1 << 11;
123
124pub const CR1_PCE_POS: u32 = 10;
125pub const CR1_PCE_WIDTH: u32 = 1;
126pub const CR1_PCE_MASK: u32 = 0x1 << 10;
127// PCE enumerated values
128pub const CR1_PCE_DISABLED: u32 = 0 << 10;
129pub const CR1_PCE_ENABLED: u32 = 1 << 10;
130
131pub const CR1_PS_POS: u32 = 9;
132pub const CR1_PS_WIDTH: u32 = 1;
133pub const CR1_PS_MASK: u32 = 0x1 << 9;
134// PS enumerated values
135pub const CR1_PS_EVEN: u32 = 0 << 9;
136pub const CR1_PS_ODD: u32 = 1 << 9;
137
138pub const CR1_PEIE_POS: u32 = 8;
139pub const CR1_PEIE_WIDTH: u32 = 1;
140pub const CR1_PEIE_MASK: u32 = 0x1 << 8;
141// PEIE enumerated values
142pub const CR1_PEIE_DISABLED: u32 = 0 << 8;
143pub const CR1_PEIE_ENABLED: u32 = 1 << 8;
144
145pub const CR1_TXEIE_POS: u32 = 7;
146pub const CR1_TXEIE_WIDTH: u32 = 1;
147pub const CR1_TXEIE_MASK: u32 = 0x1 << 7;
148// TXEIE enumerated values
149pub const CR1_TXEIE_DISABLED: u32 = 0 << 7;
150pub const CR1_TXEIE_ENABLED: u32 = 1 << 7;
151
152pub const CR1_TCIE_POS: u32 = 6;
153pub const CR1_TCIE_WIDTH: u32 = 1;
154pub const CR1_TCIE_MASK: u32 = 0x1 << 6;
155// TCIE enumerated values
156pub const CR1_TCIE_DISABLED: u32 = 0 << 6;
157pub const CR1_TCIE_ENABLED: u32 = 1 << 6;
158
159pub const CR1_RXNEIE_POS: u32 = 5;
160pub const CR1_RXNEIE_WIDTH: u32 = 1;
161pub const CR1_RXNEIE_MASK: u32 = 0x1 << 5;
162// RXNEIE enumerated values
163pub const CR1_RXNEIE_DISABLED: u32 = 0 << 5;
164pub const CR1_RXNEIE_ENABLED: u32 = 1 << 5;
165
166pub const CR1_IDLEIE_POS: u32 = 4;
167pub const CR1_IDLEIE_WIDTH: u32 = 1;
168pub const CR1_IDLEIE_MASK: u32 = 0x1 << 4;
169// IDLEIE enumerated values
170pub const CR1_IDLEIE_DISABLED: u32 = 0 << 4;
171pub const CR1_IDLEIE_ENABLED: u32 = 1 << 4;
172
173pub const CR1_TE_POS: u32 = 3;
174pub const CR1_TE_WIDTH: u32 = 1;
175pub const CR1_TE_MASK: u32 = 0x1 << 3;
176// TE enumerated values
177pub const CR1_TE_DISABLED: u32 = 0 << 3;
178pub const CR1_TE_ENABLED: u32 = 1 << 3;
179
180pub const CR1_RE_POS: u32 = 2;
181pub const CR1_RE_WIDTH: u32 = 1;
182pub const CR1_RE_MASK: u32 = 0x1 << 2;
183// RE enumerated values
184pub const CR1_RE_DISABLED: u32 = 0 << 2;
185pub const CR1_RE_ENABLED: u32 = 1 << 2;
186
187pub const CR1_RWU_POS: u32 = 1;
188pub const CR1_RWU_WIDTH: u32 = 1;
189pub const CR1_RWU_MASK: u32 = 0x1 << 1;
190// RWU enumerated values
191pub const CR1_RWU_ACTIVE: u32 = 0 << 1;
192pub const CR1_RWU_MUTE: u32 = 1 << 1;
193
194pub const CR1_SBK_POS: u32 = 0;
195pub const CR1_SBK_WIDTH: u32 = 1;
196pub const CR1_SBK_MASK: u32 = 0x1 << 0;
197// SBK enumerated values
198pub const CR1_SBK_NOBREAK: u32 = 0 << 0;
199pub const CR1_SBK_BREAK: u32 = 1 << 0;
200
201// CR2 register fields
202pub const CR2_LINEN_POS: u32 = 14;
203pub const CR2_LINEN_WIDTH: u32 = 1;
204pub const CR2_LINEN_MASK: u32 = 0x1 << 14;
205// LINEN enumerated values
206pub const CR2_LINEN_DISABLED: u32 = 0 << 14;
207pub const CR2_LINEN_ENABLED: u32 = 1 << 14;
208
209pub const CR2_STOP_POS: u32 = 12;
210pub const CR2_STOP_WIDTH: u32 = 2;
211pub const CR2_STOP_MASK: u32 = 0x3 << 12;
212// STOP enumerated values
213pub const CR2_STOP_STOP1: u32 = 0 << 12;
214pub const CR2_STOP_STOP0P5: u32 = 1 << 12;
215pub const CR2_STOP_STOP2: u32 = 2 << 12;
216pub const CR2_STOP_STOP1P5: u32 = 3 << 12;
217
218pub const CR2_CLKEN_POS: u32 = 11;
219pub const CR2_CLKEN_WIDTH: u32 = 1;
220pub const CR2_CLKEN_MASK: u32 = 0x1 << 11;
221// CLKEN enumerated values
222pub const CR2_CLKEN_DISABLED: u32 = 0 << 11;
223pub const CR2_CLKEN_ENABLED: u32 = 1 << 11;
224
225pub const CR2_CPOL_POS: u32 = 10;
226pub const CR2_CPOL_WIDTH: u32 = 1;
227pub const CR2_CPOL_MASK: u32 = 0x1 << 10;
228// CPOL enumerated values
229pub const CR2_CPOL_LOW: u32 = 0 << 10;
230pub const CR2_CPOL_HIGH: u32 = 1 << 10;
231
232pub const CR2_CPHA_POS: u32 = 9;
233pub const CR2_CPHA_WIDTH: u32 = 1;
234pub const CR2_CPHA_MASK: u32 = 0x1 << 9;
235// CPHA enumerated values
236pub const CR2_CPHA_FIRST: u32 = 0 << 9;
237pub const CR2_CPHA_SECOND: u32 = 1 << 9;
238
239pub const CR2_LBCL_POS: u32 = 8;
240pub const CR2_LBCL_WIDTH: u32 = 1;
241pub const CR2_LBCL_MASK: u32 = 0x1 << 8;
242
243pub const CR2_LBDIE_POS: u32 = 6;
244pub const CR2_LBDIE_WIDTH: u32 = 1;
245pub const CR2_LBDIE_MASK: u32 = 0x1 << 6;
246// LBDIE enumerated values
247pub const CR2_LBDIE_DISABLED: u32 = 0 << 6;
248pub const CR2_LBDIE_ENABLED: u32 = 1 << 6;
249
250pub const CR2_LBDL_POS: u32 = 5;
251pub const CR2_LBDL_WIDTH: u32 = 1;
252pub const CR2_LBDL_MASK: u32 = 0x1 << 5;
253// LBDL enumerated values
254pub const CR2_LBDL_LBDL10: u32 = 0 << 5;
255pub const CR2_LBDL_LBDL11: u32 = 1 << 5;
256
257pub const CR2_ADD_POS: u32 = 0;
258pub const CR2_ADD_WIDTH: u32 = 4;
259pub const CR2_ADD_MASK: u32 = 0xF << 0;
260
261// CR3 register fields
262pub const CR3_ONEBIT_POS: u32 = 11;
263pub const CR3_ONEBIT_WIDTH: u32 = 1;
264pub const CR3_ONEBIT_MASK: u32 = 0x1 << 11;
265// ONEBIT enumerated values
266pub const CR3_ONEBIT_SAMPLE3: u32 = 0 << 11;
267pub const CR3_ONEBIT_SAMPLE1: u32 = 1 << 11;
268
269pub const CR3_CTSIE_POS: u32 = 10;
270pub const CR3_CTSIE_WIDTH: u32 = 1;
271pub const CR3_CTSIE_MASK: u32 = 0x1 << 10;
272// CTSIE enumerated values
273pub const CR3_CTSIE_DISABLED: u32 = 0 << 10;
274pub const CR3_CTSIE_ENABLED: u32 = 1 << 10;
275
276pub const CR3_CTSE_POS: u32 = 9;
277pub const CR3_CTSE_WIDTH: u32 = 1;
278pub const CR3_CTSE_MASK: u32 = 0x1 << 9;
279// CTSE enumerated values
280pub const CR3_CTSE_DISABLED: u32 = 0 << 9;
281pub const CR3_CTSE_ENABLED: u32 = 1 << 9;
282
283pub const CR3_RTSE_POS: u32 = 8;
284pub const CR3_RTSE_WIDTH: u32 = 1;
285pub const CR3_RTSE_MASK: u32 = 0x1 << 8;
286// RTSE enumerated values
287pub const CR3_RTSE_DISABLED: u32 = 0 << 8;
288pub const CR3_RTSE_ENABLED: u32 = 1 << 8;
289
290pub const CR3_DMAT_POS: u32 = 7;
291pub const CR3_DMAT_WIDTH: u32 = 1;
292pub const CR3_DMAT_MASK: u32 = 0x1 << 7;
293// DMAT enumerated values
294pub const CR3_DMAT_DISABLED: u32 = 0 << 7;
295pub const CR3_DMAT_ENABLED: u32 = 1 << 7;
296
297pub const CR3_DMAR_POS: u32 = 6;
298pub const CR3_DMAR_WIDTH: u32 = 1;
299pub const CR3_DMAR_MASK: u32 = 0x1 << 6;
300// DMAR enumerated values
301pub const CR3_DMAR_DISABLED: u32 = 0 << 6;
302pub const CR3_DMAR_ENABLED: u32 = 1 << 6;
303
304pub const CR3_SCEN_POS: u32 = 5;
305pub const CR3_SCEN_WIDTH: u32 = 1;
306pub const CR3_SCEN_MASK: u32 = 0x1 << 5;
307// SCEN enumerated values
308pub const CR3_SCEN_DISABLED: u32 = 0 << 5;
309pub const CR3_SCEN_ENABLED: u32 = 1 << 5;
310
311pub const CR3_NACK_POS: u32 = 4;
312pub const CR3_NACK_WIDTH: u32 = 1;
313pub const CR3_NACK_MASK: u32 = 0x1 << 4;
314// NACK enumerated values
315pub const CR3_NACK_DISABLED: u32 = 0 << 4;
316pub const CR3_NACK_ENABLED: u32 = 1 << 4;
317
318pub const CR3_HDSEL_POS: u32 = 3;
319pub const CR3_HDSEL_WIDTH: u32 = 1;
320pub const CR3_HDSEL_MASK: u32 = 0x1 << 3;
321// HDSEL enumerated values
322pub const CR3_HDSEL_FULLDUPLEX: u32 = 0 << 3;
323pub const CR3_HDSEL_HALFDUPLEX: u32 = 1 << 3;
324
325pub const CR3_IRLP_POS: u32 = 2;
326pub const CR3_IRLP_WIDTH: u32 = 1;
327pub const CR3_IRLP_MASK: u32 = 0x1 << 2;
328// IRLP enumerated values
329pub const CR3_IRLP_NORMAL: u32 = 0 << 2;
330pub const CR3_IRLP_LOWPOWER: u32 = 1 << 2;
331
332pub const CR3_IREN_POS: u32 = 1;
333pub const CR3_IREN_WIDTH: u32 = 1;
334pub const CR3_IREN_MASK: u32 = 0x1 << 1;
335// IREN enumerated values
336pub const CR3_IREN_DISABLED: u32 = 0 << 1;
337pub const CR3_IREN_ENABLED: u32 = 1 << 1;
338
339pub const CR3_EIE_POS: u32 = 0;
340pub const CR3_EIE_WIDTH: u32 = 1;
341pub const CR3_EIE_MASK: u32 = 0x1 << 0;
342// EIE enumerated values
343pub const CR3_EIE_DISABLED: u32 = 0 << 0;
344pub const CR3_EIE_ENABLED: u32 = 1 << 0;
345
346// GTPR register fields
347pub const GTPR_GT_POS: u32 = 8;
348pub const GTPR_GT_WIDTH: u32 = 8;
349pub const GTPR_GT_MASK: u32 = 0xFF << 8;
350
351pub const GTPR_PSC_POS: u32 = 0;
352pub const GTPR_PSC_WIDTH: u32 = 8;
353pub const GTPR_PSC_MASK: u32 = 0xFF << 0;
354
355// Helper functions for USART
356impl RegisterBlock {
357    /// Enable USART
358    pub fn enable(&mut self) {
359        self.cr1 |= CR1_UE_MASK;
360    }
361
362    /// Disable USART
363    pub fn disable(&mut self) {
364        self.cr1 &= !CR1_UE_MASK;
365    }
366
367    /// Enable transmitter
368    pub fn enable_tx(&mut self) {
369        self.cr1 |= CR1_TE_MASK;
370    }
371
372    /// Enable receiver
373    pub fn enable_rx(&mut self) {
374        self.cr1 |= CR1_RE_MASK;
375    }
376
377    /// Set baud rate
378    pub fn set_baud_rate(&mut self, brr_value: u32) {
379        self.brr = brr_value & 0xFFFF;
380    }
381
382    /// Check if transmit buffer is empty
383    pub fn is_tx_empty(&self) -> bool {
384        (self.sr & SR_TXE_MASK) != 0
385    }
386
387    /// Check if data is received
388    pub fn is_rx_not_empty(&self) -> bool {
389        (self.sr & SR_RXNE_MASK) != 0
390    }
391
392    /// Write data
393    pub fn write_data(&mut self, data: u8) {
394        self.dr = data as u32;
395    }
396
397    /// Read data
398    pub fn read_data(&self) -> u8 {
399        (self.dr & 0xFF) as u8
400    }
401}
stm32_rust_template/mcu/stm32f407/usart.rs

stm32_rust_template/mcu/stm32f407/
usart.rs
