stm32_rust_template/mcu/stm32f407/
rcc.rs

1// RCC (Reset and Clock Control) peripheral definitions
2// Generated from STM32F407 SVD file
3
4use super::{PeripheralAccess, RCC_BASEADDR};
5
6// RCC Register Block
7#[repr(C)]
8pub struct RegisterBlock {
9    pub cr: u32,       // RW: clock control register
10    pub pllcfgr: u32,  // RW: PLL configuration register
11    pub cfgr: u32,     // RW: clock configuration register
12    pub cir: u32,      // RW: clock interrupt register
13    pub ahb1rstr: u32, // RW: AHB1 peripheral reset register
14    pub ahb2rstr: u32, // RW: AHB2 peripheral reset register
15    pub ahb3rstr: u32, // RW: AHB3 peripheral reset register
16    _reserved0: u32,
17    pub apb1rstr: u32, // RW: APB1 peripheral reset register
18    pub apb2rstr: u32, // RW: APB2 peripheral reset register
19    _reserved1: [u32; 2],
20    pub ahb1enr: u32, // RW: AHB1 peripheral clock register
21    pub ahb2enr: u32, // RW: AHB2 peripheral clock enable register
22    pub ahb3enr: u32, // RW: AHB3 peripheral clock enable register
23    _reserved2: u32,
24    pub apb1enr: u32, // RW: APB1 peripheral clock enable register
25    pub apb2enr: u32, // RW: APB2 peripheral clock enable register
26    _reserved3: [u32; 2],
27    pub ahb1lpenr: u32, // RW: AHB1 peripheral clock enable in low power mode register
28    pub ahb2lpenr: u32, // RW: AHB2 peripheral clock enable in low power mode register
29    pub ahb3lpenr: u32, // RW: AHB3 peripheral clock enable in low power mode register
30    _reserved4: u32,
31    pub apb1lpenr: u32, // RW: APB1 peripheral clock enable in low power mode register
32    pub apb2lpenr: u32, // RW: APB2 peripheral clock enabled in low power mode register
33    _reserved5: [u32; 2],
34    pub bdcr: u32, // RW: Backup domain control register
35    pub csr: u32,  // RW: clock control & status register
36    _reserved6: [u32; 2],
37    pub sscgr: u32,      // RW: spread spectrum clock generation register
38    pub plli2scfgr: u32, // RW: PLLI2S configuration register
39}
40
41impl PeripheralAccess for RegisterBlock {
42    const BASE_ADDRESS: u32 = RCC_BASEADDR;
43    type RegisterBlock = RegisterBlock;
44}
45
46// RCC Register Field Definitions
47
48// CR register fields
49pub const CR_PLLI2SRDY_POS: u32 = 27;
50pub const CR_PLLI2SRDY_WIDTH: u32 = 1;
51pub const CR_PLLI2SRDY_MASK: u32 = 0x1 << 27;
52
53pub const CR_PLLI2SON_POS: u32 = 26;
54pub const CR_PLLI2SON_WIDTH: u32 = 1;
55pub const CR_PLLI2SON_MASK: u32 = 0x1 << 26;
56
57pub const CR_PLLRDY_POS: u32 = 25;
58pub const CR_PLLRDY_WIDTH: u32 = 1;
59pub const CR_PLLRDY_MASK: u32 = 0x1 << 25;
60
61pub const CR_PLLON_POS: u32 = 24;
62pub const CR_PLLON_WIDTH: u32 = 1;
63pub const CR_PLLON_MASK: u32 = 0x1 << 24;
64
65pub const CR_CSSON_POS: u32 = 19;
66pub const CR_CSSON_WIDTH: u32 = 1;
67pub const CR_CSSON_MASK: u32 = 0x1 << 19;
68// CSSON enumerated values
69pub const CR_CSSON_OFF: u32 = 0 << 19;
70pub const CR_CSSON_ON: u32 = 1 << 19;
71
72pub const CR_HSEBYP_POS: u32 = 18;
73pub const CR_HSEBYP_WIDTH: u32 = 1;
74pub const CR_HSEBYP_MASK: u32 = 0x1 << 18;
75// HSEBYP enumerated values
76pub const CR_HSEBYP_NOTBYPASSED: u32 = 0 << 18;
77pub const CR_HSEBYP_BYPASSED: u32 = 1 << 18;
78
79pub const CR_HSERDY_POS: u32 = 17;
80pub const CR_HSERDY_WIDTH: u32 = 1;
81pub const CR_HSERDY_MASK: u32 = 0x1 << 17;
82
83pub const CR_HSEON_POS: u32 = 16;
84pub const CR_HSEON_WIDTH: u32 = 1;
85pub const CR_HSEON_MASK: u32 = 0x1 << 16;
86
87pub const CR_HSICAL_POS: u32 = 8;
88pub const CR_HSICAL_WIDTH: u32 = 8;
89pub const CR_HSICAL_MASK: u32 = 0xFF << 8;
90
91pub const CR_HSITRIM_POS: u32 = 3;
92pub const CR_HSITRIM_WIDTH: u32 = 5;
93pub const CR_HSITRIM_MASK: u32 = 0x1F << 3;
94
95pub const CR_HSIRDY_POS: u32 = 1;
96pub const CR_HSIRDY_WIDTH: u32 = 1;
97pub const CR_HSIRDY_MASK: u32 = 0x1 << 1;
98// HSIRDY enumerated values
99pub const CR_HSIRDY_NOTREADY: u32 = 0 << 1;
100pub const CR_HSIRDY_READY: u32 = 1 << 1;
101
102pub const CR_HSION_POS: u32 = 0;
103pub const CR_HSION_WIDTH: u32 = 1;
104pub const CR_HSION_MASK: u32 = 0x1 << 0;
105// HSION enumerated values
106pub const CR_HSION_OFF: u32 = 0 << 0;
107pub const CR_HSION_ON: u32 = 1 << 0;
108
109// PLLCFGR register fields
110pub const PLLCFGR_PLLSRC_POS: u32 = 22;
111pub const PLLCFGR_PLLSRC_WIDTH: u32 = 1;
112pub const PLLCFGR_PLLSRC_MASK: u32 = 0x1 << 22;
113// PLLSRC enumerated values
114pub const PLLCFGR_PLLSRC_HSI: u32 = 0 << 22;
115pub const PLLCFGR_PLLSRC_HSE: u32 = 1 << 22;
116
117pub const PLLCFGR_PLLM_POS: u32 = 0;
118pub const PLLCFGR_PLLM_WIDTH: u32 = 6;
119pub const PLLCFGR_PLLM_MASK: u32 = 0x3F << 0;
120
121pub const PLLCFGR_PLLN_POS: u32 = 6;
122pub const PLLCFGR_PLLN_WIDTH: u32 = 9;
123pub const PLLCFGR_PLLN_MASK: u32 = 0x1FF << 6;
124
125pub const PLLCFGR_PLLP_POS: u32 = 16;
126pub const PLLCFGR_PLLP_WIDTH: u32 = 2;
127pub const PLLCFGR_PLLP_MASK: u32 = 0x3 << 16;
128// PLLP enumerated values
129pub const PLLCFGR_PLLP_DIV2: u32 = 0 << 16;
130pub const PLLCFGR_PLLP_DIV4: u32 = 1 << 16;
131pub const PLLCFGR_PLLP_DIV6: u32 = 2 << 16;
132pub const PLLCFGR_PLLP_DIV8: u32 = 3 << 16;
133
134pub const PLLCFGR_PLLQ_POS: u32 = 24;
135pub const PLLCFGR_PLLQ_WIDTH: u32 = 4;
136pub const PLLCFGR_PLLQ_MASK: u32 = 0xF << 24;
137
138// CFGR register fields
139pub const CFGR_MCO2_POS: u32 = 30;
140pub const CFGR_MCO2_WIDTH: u32 = 2;
141pub const CFGR_MCO2_MASK: u32 = 0x3 << 30;
142// MCO2 enumerated values
143pub const CFGR_MCO2_SYSCLK: u32 = 0 << 30;
144pub const CFGR_MCO2_PLLI2S: u32 = 1 << 30;
145pub const CFGR_MCO2_HSE: u32 = 2 << 30;
146pub const CFGR_MCO2_PLL: u32 = 3 << 30;
147
148pub const CFGR_MCO2PRE_POS: u32 = 27;
149pub const CFGR_MCO2PRE_WIDTH: u32 = 3;
150pub const CFGR_MCO2PRE_MASK: u32 = 0x7 << 27;
151// MCO2PRE enumerated values
152pub const CFGR_MCO2PRE_DIV1: u32 = 0 << 27;
153pub const CFGR_MCO2PRE_DIV2: u32 = 4 << 27;
154pub const CFGR_MCO2PRE_DIV3: u32 = 5 << 27;
155pub const CFGR_MCO2PRE_DIV4: u32 = 6 << 27;
156pub const CFGR_MCO2PRE_DIV5: u32 = 7 << 27;
157
158pub const CFGR_MCO1PRE_POS: u32 = 24;
159pub const CFGR_MCO1PRE_WIDTH: u32 = 3;
160pub const CFGR_MCO1PRE_MASK: u32 = 0x7 << 24;
161// MCO1PRE enumerated values
162pub const CFGR_MCO1PRE_DIV1: u32 = 0 << 24;
163pub const CFGR_MCO1PRE_DIV2: u32 = 4 << 24;
164pub const CFGR_MCO1PRE_DIV3: u32 = 5 << 24;
165pub const CFGR_MCO1PRE_DIV4: u32 = 6 << 24;
166pub const CFGR_MCO1PRE_DIV5: u32 = 7 << 24;
167
168pub const CFGR_MCO1_POS: u32 = 21;
169pub const CFGR_MCO1_WIDTH: u32 = 2;
170pub const CFGR_MCO1_MASK: u32 = 0x3 << 21;
171// MCO1 enumerated values
172pub const CFGR_MCO1_HSI: u32 = 0 << 21;
173pub const CFGR_MCO1_LSE: u32 = 1 << 21;
174pub const CFGR_MCO1_HSE: u32 = 2 << 21;
175pub const CFGR_MCO1_PLL: u32 = 3 << 21;
176
177pub const CFGR_RTCPRE_POS: u32 = 16;
178pub const CFGR_RTCPRE_WIDTH: u32 = 5;
179pub const CFGR_RTCPRE_MASK: u32 = 0x1F << 16;
180
181pub const CFGR_PPRE2_POS: u32 = 13;
182pub const CFGR_PPRE2_WIDTH: u32 = 3;
183pub const CFGR_PPRE2_MASK: u32 = 0x7 << 13;
184// PPRE2 enumerated values
185pub const CFGR_PPRE2_DIV1: u32 = 0 << 13;
186pub const CFGR_PPRE2_DIV2: u32 = 4 << 13;
187pub const CFGR_PPRE2_DIV4: u32 = 5 << 13;
188pub const CFGR_PPRE2_DIV8: u32 = 6 << 13;
189pub const CFGR_PPRE2_DIV16: u32 = 7 << 13;
190
191pub const CFGR_PPRE1_POS: u32 = 10;
192pub const CFGR_PPRE1_WIDTH: u32 = 3;
193pub const CFGR_PPRE1_MASK: u32 = 0x7 << 10;
194// PPRE1 enumerated values
195pub const CFGR_PPRE1_DIV1: u32 = 0 << 10;
196pub const CFGR_PPRE1_DIV2: u32 = 4 << 10;
197pub const CFGR_PPRE1_DIV4: u32 = 5 << 10;
198pub const CFGR_PPRE1_DIV8: u32 = 6 << 10;
199pub const CFGR_PPRE1_DIV16: u32 = 7 << 10;
200
201pub const CFGR_HPRE_POS: u32 = 4;
202pub const CFGR_HPRE_WIDTH: u32 = 4;
203pub const CFGR_HPRE_MASK: u32 = 0xF << 4;
204// HPRE enumerated values
205pub const CFGR_HPRE_DIV1: u32 = 0 << 4;
206pub const CFGR_HPRE_DIV2: u32 = 8 << 4;
207pub const CFGR_HPRE_DIV4: u32 = 9 << 4;
208pub const CFGR_HPRE_DIV8: u32 = 10 << 4;
209pub const CFGR_HPRE_DIV16: u32 = 11 << 4;
210pub const CFGR_HPRE_DIV64: u32 = 12 << 4;
211pub const CFGR_HPRE_DIV128: u32 = 13 << 4;
212pub const CFGR_HPRE_DIV256: u32 = 14 << 4;
213pub const CFGR_HPRE_DIV512: u32 = 15 << 4;
214
215pub const CFGR_SWS_POS: u32 = 2;
216pub const CFGR_SWS_WIDTH: u32 = 2;
217pub const CFGR_SWS_MASK: u32 = 0x3 << 2;
218// SWS enumerated values
219pub const CFGR_SWS_HSI: u32 = 0 << 2;
220pub const CFGR_SWS_HSE: u32 = 1 << 2;
221pub const CFGR_SWS_PLL: u32 = 2 << 2;
222
223pub const CFGR_SW_POS: u32 = 0;
224pub const CFGR_SW_WIDTH: u32 = 2;
225pub const CFGR_SW_MASK: u32 = 0x3 << 0;
226// SW enumerated values
227pub const CFGR_SW_HSI: u32 = 0 << 0;
228pub const CFGR_SW_HSE: u32 = 1 << 0;
229pub const CFGR_SW_PLL: u32 = 2 << 0;
230
231// AHB1ENR register fields
232pub const AHB1ENR_DMA2EN_POS: u32 = 22;
233pub const AHB1ENR_DMA2EN_WIDTH: u32 = 1;
234pub const AHB1ENR_DMA2EN_MASK: u32 = 0x1 << 22;
235
236pub const AHB1ENR_DMA1EN_POS: u32 = 21;
237pub const AHB1ENR_DMA1EN_WIDTH: u32 = 1;
238pub const AHB1ENR_DMA1EN_MASK: u32 = 0x1 << 21;
239
240pub const AHB1ENR_CRCEN_POS: u32 = 12;
241pub const AHB1ENR_CRCEN_WIDTH: u32 = 1;
242pub const AHB1ENR_CRCEN_MASK: u32 = 0x1 << 12;
243
244pub const AHB1ENR_GPIOIEN_POS: u32 = 8;
245pub const AHB1ENR_GPIOIEN_WIDTH: u32 = 1;
246pub const AHB1ENR_GPIOIEN_MASK: u32 = 0x1 << 8;
247
248pub const AHB1ENR_GPIOHEN_POS: u32 = 7;
249pub const AHB1ENR_GPIOHEN_WIDTH: u32 = 1;
250pub const AHB1ENR_GPIOHEN_MASK: u32 = 0x1 << 7;
251
252pub const AHB1ENR_GPIOGEN_POS: u32 = 6;
253pub const AHB1ENR_GPIOGEN_WIDTH: u32 = 1;
254pub const AHB1ENR_GPIOGEN_MASK: u32 = 0x1 << 6;
255
256pub const AHB1ENR_GPIOFEN_POS: u32 = 5;
257pub const AHB1ENR_GPIOFEN_WIDTH: u32 = 1;
258pub const AHB1ENR_GPIOFEN_MASK: u32 = 0x1 << 5;
259
260pub const AHB1ENR_GPIOEEN_POS: u32 = 4;
261pub const AHB1ENR_GPIOEEN_WIDTH: u32 = 1;
262pub const AHB1ENR_GPIOEEN_MASK: u32 = 0x1 << 4;
263
264pub const AHB1ENR_GPIODEN_POS: u32 = 3;
265pub const AHB1ENR_GPIODEN_WIDTH: u32 = 1;
266pub const AHB1ENR_GPIODEN_MASK: u32 = 0x1 << 3;
267
268pub const AHB1ENR_GPIOCEN_POS: u32 = 2;
269pub const AHB1ENR_GPIOCEN_WIDTH: u32 = 1;
270pub const AHB1ENR_GPIOCEN_MASK: u32 = 0x1 << 2;
271
272pub const AHB1ENR_GPIOBEN_POS: u32 = 1;
273pub const AHB1ENR_GPIOBEN_WIDTH: u32 = 1;
274pub const AHB1ENR_GPIOBEN_MASK: u32 = 0x1 << 1;
275
276pub const AHB1ENR_GPIOAEN_POS: u32 = 0;
277pub const AHB1ENR_GPIOAEN_WIDTH: u32 = 1;
278pub const AHB1ENR_GPIOAEN_MASK: u32 = 0x1 << 0;
279
280// APB1ENR register fields
281pub const APB1ENR_UART8EN_POS: u32 = 31;
282pub const APB1ENR_UART8EN_WIDTH: u32 = 1;
283pub const APB1ENR_UART8EN_MASK: u32 = 0x1 << 31;
284
285pub const APB1ENR_UART7EN_POS: u32 = 30;
286pub const APB1ENR_UART7EN_WIDTH: u32 = 1;
287pub const APB1ENR_UART7EN_MASK: u32 = 0x1 << 30;
288
289pub const APB1ENR_DACEN_POS: u32 = 29;
290pub const APB1ENR_DACEN_WIDTH: u32 = 1;
291pub const APB1ENR_DACEN_MASK: u32 = 0x1 << 29;
292
293pub const APB1ENR_PWREN_POS: u32 = 28;
294pub const APB1ENR_PWREN_WIDTH: u32 = 1;
295pub const APB1ENR_PWREN_MASK: u32 = 0x1 << 28;
296
297pub const APB1ENR_CAN2EN_POS: u32 = 26;
298pub const APB1ENR_CAN2EN_WIDTH: u32 = 1;
299pub const APB1ENR_CAN2EN_MASK: u32 = 0x1 << 26;
300
301pub const APB1ENR_CAN1EN_POS: u32 = 25;
302pub const APB1ENR_CAN1EN_WIDTH: u32 = 1;
303pub const APB1ENR_CAN1EN_MASK: u32 = 0x1 << 25;
304
305pub const APB1ENR_I2C3EN_POS: u32 = 23;
306pub const APB1ENR_I2C3EN_WIDTH: u32 = 1;
307pub const APB1ENR_I2C3EN_MASK: u32 = 0x1 << 23;
308
309pub const APB1ENR_I2C2EN_POS: u32 = 22;
310pub const APB1ENR_I2C2EN_WIDTH: u32 = 1;
311pub const APB1ENR_I2C2EN_MASK: u32 = 0x1 << 22;
312
313pub const APB1ENR_I2C1EN_POS: u32 = 21;
314pub const APB1ENR_I2C1EN_WIDTH: u32 = 1;
315pub const APB1ENR_I2C1EN_MASK: u32 = 0x1 << 21;
316
317pub const APB1ENR_UART5EN_POS: u32 = 20;
318pub const APB1ENR_UART5EN_WIDTH: u32 = 1;
319pub const APB1ENR_UART5EN_MASK: u32 = 0x1 << 20;
320
321pub const APB1ENR_UART4EN_POS: u32 = 19;
322pub const APB1ENR_UART4EN_WIDTH: u32 = 1;
323pub const APB1ENR_UART4EN_MASK: u32 = 0x1 << 19;
324
325pub const APB1ENR_USART3EN_POS: u32 = 18;
326pub const APB1ENR_USART3EN_WIDTH: u32 = 1;
327pub const APB1ENR_USART3EN_MASK: u32 = 0x1 << 18;
328
329pub const APB1ENR_USART2EN_POS: u32 = 17;
330pub const APB1ENR_USART2EN_WIDTH: u32 = 1;
331pub const APB1ENR_USART2EN_MASK: u32 = 0x1 << 17;
332
333pub const APB1ENR_SPI3EN_POS: u32 = 15;
334pub const APB1ENR_SPI3EN_WIDTH: u32 = 1;
335pub const APB1ENR_SPI3EN_MASK: u32 = 0x1 << 15;
336
337pub const APB1ENR_SPI2EN_POS: u32 = 14;
338pub const APB1ENR_SPI2EN_WIDTH: u32 = 1;
339pub const APB1ENR_SPI2EN_MASK: u32 = 0x1 << 14;
340
341pub const APB1ENR_WWDGEN_POS: u32 = 11;
342pub const APB1ENR_WWDGEN_WIDTH: u32 = 1;
343pub const APB1ENR_WWDGEN_MASK: u32 = 0x1 << 11;
344
345pub const APB1ENR_TIM14EN_POS: u32 = 8;
346pub const APB1ENR_TIM14EN_WIDTH: u32 = 1;
347pub const APB1ENR_TIM14EN_MASK: u32 = 0x1 << 8;
348
349pub const APB1ENR_TIM13EN_POS: u32 = 7;
350pub const APB1ENR_TIM13EN_WIDTH: u32 = 1;
351pub const APB1ENR_TIM13EN_MASK: u32 = 0x1 << 7;
352
353pub const APB1ENR_TIM12EN_POS: u32 = 6;
354pub const APB1ENR_TIM12EN_WIDTH: u32 = 1;
355pub const APB1ENR_TIM12EN_MASK: u32 = 0x1 << 6;
356
357pub const APB1ENR_TIM7EN_POS: u32 = 5;
358pub const APB1ENR_TIM7EN_WIDTH: u32 = 1;
359pub const APB1ENR_TIM7EN_MASK: u32 = 0x1 << 5;
360
361pub const APB1ENR_TIM6EN_POS: u32 = 4;
362pub const APB1ENR_TIM6EN_WIDTH: u32 = 1;
363pub const APB1ENR_TIM6EN_MASK: u32 = 0x1 << 4;
364
365pub const APB1ENR_TIM5EN_POS: u32 = 3;
366pub const APB1ENR_TIM5EN_WIDTH: u32 = 1;
367pub const APB1ENR_TIM5EN_MASK: u32 = 0x1 << 3;
368
369pub const APB1ENR_TIM4EN_POS: u32 = 2;
370pub const APB1ENR_TIM4EN_WIDTH: u32 = 1;
371pub const APB1ENR_TIM4EN_MASK: u32 = 0x1 << 2;
372
373pub const APB1ENR_TIM3EN_POS: u32 = 1;
374pub const APB1ENR_TIM3EN_WIDTH: u32 = 1;
375pub const APB1ENR_TIM3EN_MASK: u32 = 0x1 << 1;
376
377pub const APB1ENR_TIM2EN_POS: u32 = 0;
378pub const APB1ENR_TIM2EN_WIDTH: u32 = 1;
379pub const APB1ENR_TIM2EN_MASK: u32 = 0x1 << 0;
380
381// APB2ENR register fields
382pub const APB2ENR_LTDCEN_POS: u32 = 26;
383pub const APB2ENR_LTDCEN_WIDTH: u32 = 1;
384pub const APB2ENR_LTDCEN_MASK: u32 = 0x1 << 26;
385
386pub const APB2ENR_SAI1EN_POS: u32 = 22;
387pub const APB2ENR_SAI1EN_WIDTH: u32 = 1;
388pub const APB2ENR_SAI1EN_MASK: u32 = 0x1 << 22;
389
390pub const APB2ENR_SPI6EN_POS: u32 = 21;
391pub const APB2ENR_SPI6EN_WIDTH: u32 = 1;
392pub const APB2ENR_SPI6EN_MASK: u32 = 0x1 << 21;
393
394pub const APB2ENR_SPI5EN_POS: u32 = 20;
395pub const APB2ENR_SPI5EN_WIDTH: u32 = 1;
396pub const APB2ENR_SPI5EN_MASK: u32 = 0x1 << 20;
397
398pub const APB2ENR_TIM11EN_POS: u32 = 18;
399pub const APB2ENR_TIM11EN_WIDTH: u32 = 1;
400pub const APB2ENR_TIM11EN_MASK: u32 = 0x1 << 18;
401
402pub const APB2ENR_TIM10EN_POS: u32 = 17;
403pub const APB2ENR_TIM10EN_WIDTH: u32 = 1;
404pub const APB2ENR_TIM10EN_MASK: u32 = 0x1 << 17;
405
406pub const APB2ENR_TIM9EN_POS: u32 = 16;
407pub const APB2ENR_TIM9EN_WIDTH: u32 = 1;
408pub const APB2ENR_TIM9EN_MASK: u32 = 0x1 << 16;
409
410pub const APB2ENR_EXTITEN_POS: u32 = 14;
411pub const APB2ENR_EXTITEN_WIDTH: u32 = 1;
412pub const APB2ENR_EXTITEN_MASK: u32 = 0x1 << 14;
413
414pub const APB2ENR_SYSCFGEN_POS: u32 = 14;
415pub const APB2ENR_SYSCFGEN_WIDTH: u32 = 1;
416pub const APB2ENR_SYSCFGEN_MASK: u32 = 0x1 << 14;
417
418pub const APB2ENR_SPI4EN_POS: u32 = 13;
419pub const APB2ENR_SPI4EN_WIDTH: u32 = 1;
420pub const APB2ENR_SPI4EN_MASK: u32 = 0x1 << 13;
421
422pub const APB2ENR_SPI1EN_POS: u32 = 12;
423pub const APB2ENR_SPI1EN_WIDTH: u32 = 1;
424pub const APB2ENR_SPI1EN_MASK: u32 = 0x1 << 12;
425
426pub const APB2ENR_SDIOEN_POS: u32 = 11;
427pub const APB2ENR_SDIOEN_WIDTH: u32 = 1;
428pub const APB2ENR_SDIOEN_MASK: u32 = 0x1 << 11;
429
430pub const APB2ENR_ADC3EN_POS: u32 = 10;
431pub const APB2ENR_ADC3EN_WIDTH: u32 = 1;
432pub const APB2ENR_ADC3EN_MASK: u32 = 0x1 << 10;
433
434pub const APB2ENR_ADC2EN_POS: u32 = 9;
435pub const APB2ENR_ADC2EN_WIDTH: u32 = 1;
436pub const APB2ENR_ADC2EN_MASK: u32 = 0x1 << 9;
437
438pub const APB2ENR_ADC1EN_POS: u32 = 8;
439pub const APB2ENR_ADC1EN_WIDTH: u32 = 1;
440pub const APB2ENR_ADC1EN_MASK: u32 = 0x1 << 8;
441
442pub const APB2ENR_USART6EN_POS: u32 = 5;
443pub const APB2ENR_USART6EN_WIDTH: u32 = 1;
444pub const APB2ENR_USART6EN_MASK: u32 = 0x1 << 5;
445
446pub const APB2ENR_USART1EN_POS: u32 = 4;
447pub const APB2ENR_USART1EN_WIDTH: u32 = 1;
448pub const APB2ENR_USART1EN_MASK: u32 = 0x1 << 4;
449
450pub const APB2ENR_TIM8EN_POS: u32 = 1;
451pub const APB2ENR_TIM8EN_WIDTH: u32 = 1;
452pub const APB2ENR_TIM8EN_MASK: u32 = 0x1 << 1;
453
454pub const APB2ENR_TIM1EN_POS: u32 = 0;
455pub const APB2ENR_TIM1EN_WIDTH: u32 = 1;
456pub const APB2ENR_TIM1EN_MASK: u32 = 0x1 << 0;
457
458// RCC peripheral instance
459pub type RCC = RegisterBlock;
stm32_rust_template/mcu/stm32f407/rcc.rs

stm32_rust_template/mcu/stm32f407/
rcc.rs
