stm32_rust_template/driver/usart/
mod.rs

1//! # USART Driver
2//!
3//! Provides a hardware abstraction layer for Universal Synchronous/Asynchronous
4//! Receiver/Transmitter (USART) communication on STM32 microcontrollers.
5//!
6//! This module defines the USART trait and supporting types for serial
7//! communication including UART, synchronous modes, and modem control
8//! across different STM32 families.
9#![allow(dead_code)]
10
11use bitflags::bitflags;
12use core::ops::FnMut;
13
14/// Defines the possible modes for USART communication.
15#[derive(Debug, Clone, Copy, PartialEq, Eq)]
16pub enum Mode {
17    /// UART (Asynchronous)
18    Asynchronous,
19    /// Synchronous Master (generates clock signal)
20    SynchronousMaster,
21    /// Synchronous Slave (external clock signal)
22    SynchronousSlave,
23    /// UART Single-wire (half-duplex)
24    SingleWire,
25    /// UART IrDA
26    IrDA,
27    /// UART Smart Card
28    SmartCard,
29}
30
31/// Defines the number of data bits in a frame.
32#[derive(Debug, Clone, Copy, PartialEq, Eq)]
33pub enum DataBits {
34    Bits5 = 5,
35    Bits6 = 6,
36    Bits7 = 7,
37    /// Default
38    Bits8 = 8,
39    Bits9 = 9,
40}
41
42/// Defines the parity generation and checking.
43#[derive(Debug, Clone, Copy, PartialEq, Eq)]
44pub enum Parity {
45    /// Default
46    None,
47    Even,
48    Odd,
49}
50
51/// Defines the number of stop bits.
52#[derive(Debug, Clone, Copy, PartialEq, Eq)]
53pub enum StopBits {
54    /// Default
55    Bits1,
56    Bits2,
57    Bits1_5,
58    Bits0_5,
59}
60
61/// Defines the flow control type.
62#[derive(Debug, Clone, Copy, PartialEq, Eq)]
63pub enum FlowControl {
64    /// Default
65    None,
66    RTS,
67    CTS,
68    RTS_CTS,
69}
70
71/// Defines the clock polarity for synchronous modes.
72#[derive(Debug, Clone, Copy, PartialEq, Eq)]
73pub enum ClockPolarity {
74    /// Default
75    CPOL0,
76    CPOL1,
77}
78
79/// Defines the clock phase for synchronous modes.
80#[derive(Debug, Clone, Copy, PartialEq, Eq)]
81pub enum ClockPhase {
82    /// Default
83    CPHA0,
84    CPHA1,
85}
86
87/// Defines the modem control lines.
88#[derive(Debug, Clone, Copy, PartialEq, Eq)]
89pub enum ModemControl {
90    RTSClear,
91    RTSSet,
92    DTRClear,
93    DTRSet,
94}
95
96/// Represents the status of the USART peripheral.
97#[derive(Debug, Clone, Copy, PartialEq, Eq)]
98pub struct Status {
99    /// Transmitter busy flag
100    pub tx_busy: bool,
101    /// Receiver busy flag
102    pub rx_busy: bool,
103    /// Transmit data underflow detected
104    pub tx_underflow: bool,
105    /// Receive data overflow detected
106    pub rx_overflow: bool,
107    /// Break detected on receive
108    pub rx_break: bool,
109    /// Framing error detected on receive
110    pub rx_framing_error: bool,
111    /// Parity error detected on receive
112    pub rx_parity_error: bool,
113}
114
115/// Represents the status of the modem signals.
116#[derive(Debug, Clone, Copy, PartialEq, Eq)]
117pub struct ModemStatus {
118    /// CTS state: true=Active, false=Inactive
119    pub cts: bool,
120    /// DSR state: true=Active, false=Inactive
121    pub dsr: bool,
122    /// DCD state: true=Active, false=Inactive
123    pub dcd: bool,
124    /// RI state: true=Active, false=Inactive
125    pub ri: bool,
126}
127
128bitflags! {
129    /// Represents USART communication events.
130    #[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)]
131    pub struct Event: u32 {
132        /// Send completed
133        const SEND_COMPLETE = (1 << 0);
134        /// Receive completed
135        const RECEIVE_COMPLETE = (1 << 1);
136        /// Transfer completed
137        const TRANSFER_COMPLETE = (1 << 2);
138        /// Transmit completed
139        const TX_COMPLETE = (1 << 3);
140        /// Transmit data not available
141        const TX_UNDERFLOW = (1 << 4);
142        /// Receive data overflow
143        const RX_OVERFLOW = (1 << 5);
144        /// Receive character timeout
145        const RX_TIMEOUT = (1 << 6);
146        /// Break detected on receive
147        const RX_BREAK = (1 << 7);
148        /// Framing error detected on receive
149        const RX_FRAMING_ERROR = (1 << 8);
150        /// Parity error detected on receive
151        const RX_PARITY_ERROR = (1 << 9);
152        /// CTS state changed
153        const CTS = (1 << 10);
154        /// DSR state changed
155        const DSR = (1 << 11);
156        /// DCD state changed
157        const DCD = (1 << 12);
158        /// RI state changed
159        const RI = (1 << 13);
160    }
161}
162
163/// A generic error type for the USART driver, using i32 for error codes.
164pub type Error = i32;
165
166/// A specialized Result type for USART operations.
167pub type Result<T> = core::result::Result<T, Error>;
168
169/// Holds the configuration for a USART peripheral.
170#[derive(Debug, Clone, PartialEq, Eq)]
171pub struct Config {
172    pub mode: Mode,
173    pub baudrate: u32,
174    pub data_bits: DataBits,
175    pub parity: Parity,
176    pub stop_bits: StopBits,
177    pub flow_control: FlowControl,
178    /// For synchronous modes
179    pub clock_polarity: ClockPolarity,
180    /// For synchronous modes
181    pub clock_phase: ClockPhase,
182}
183
184impl Default for Config {
185    fn default() -> Self {
186        Self {
187            mode: Mode::Asynchronous,
188            baudrate: 115200,
189            data_bits: DataBits::Bits8,
190            parity: Parity::None,
191            stop_bits: StopBits::Bits1,
192            flow_control: FlowControl::None,
193            clock_polarity: ClockPolarity::CPOL0,
194            clock_phase: ClockPhase::CPHA0,
195        }
196    }
197}
198
199/// A trait that defines a standard interface for a USART driver.
200pub trait Usart<'a> {
201    /// Initializes the USART peripheral.
202    ///
203    /// The provided callback will be invoked to signal communication events.
204    fn initialize(&mut self, callback: impl FnMut(Event) + 'a) -> Result<()>;
205
206    /// De-initializes the USART peripheral.
207    fn uninitialize(&mut self) -> Result<()>;
208
209    /// Configures the USART peripheral.
210    fn configure(&mut self, config: &Config) -> Result<()>;
211
212    /// Transmits data over the USART bus.
213    fn send(&mut self, data: &[u8]) -> Result<()>;
214
215    /// Receives data from the USART bus.
216    fn receive(&mut self, data: &mut [u8]) -> Result<()>;
217
218    /// Simultaneously sends and receives data.
219    fn transfer(&mut self, data_out: &[u8], data_in: &mut [u8]) -> Result<()>;
220
221    /// Gets the number of bytes transmitted.
222    fn get_tx_count(&self) -> u32;
223
224    /// Gets the number of bytes received.
225    fn get_rx_count(&self) -> u32;
226
227    /// Gets the current status of the USART peripheral.
228    fn get_status(&self) -> Status;
229
230    /// Controls the modem lines.
231    fn set_modem_control(&mut self, control: ModemControl) -> Result<()>;
232
233    /// Gets the status of the modem lines.
234    fn get_modem_status(&self) -> ModemStatus;
235
236    /// Enables or disables the transmitter.
237    fn tx_enable(&mut self, enable: bool) -> Result<()>;
238
239    /// Enables or disables the receiver.
240    fn rx_enable(&mut self, enable: bool) -> Result<()>;
241
242    /// Controls the generation of a break condition.
243    fn control_break(&mut self, enable: bool) -> Result<()>;
244
245    /// Aborts an ongoing send operation.
246    fn abort_send(&mut self) -> Result<()>;
247
248    /// Aborts an ongoing receive operation.
249    fn abort_receive(&mut self) -> Result<()>;
250
251    /// Aborts an ongoing transfer operation.
252    fn abort_transfer(&mut self) -> Result<()>;
253}
254
255#[cfg(feature = "stm32f407")]
256pub mod stm32f407;
257
258#[cfg(feature = "stm32f401")]
259pub mod stm32f401;
260
261#[cfg(feature = "stm32f411")]
262pub mod stm32f411;
263
264#[cfg(feature = "stm32f103")]
265pub mod stm32f103;
stm32_rust_template/driver/usart/mod.rs

stm32_rust_template/driver/usart/
mod.rs
