stm32_rust_template/arch/cortex_m4/
scb.rs

1// SCB (System Control Block) register definitions
2// Based on CMSIS Cortex-M4 core_cm4.h
3
4use super::super::super::mcu::stm32f407::PeripheralAccess;
5
6// SCB Base Address
7pub const SCB_BASE: u32 = 0xE000ED00;
8
9// SCB Register Block
10#[repr(C)]
11pub struct Scb {
12    pub cpuid: u32,     // CPUID Base Register
13    pub icsr: u32,      // Interrupt Control and State Register
14    pub vtor: u32,      // Vector Table Offset Register
15    pub aircr: u32,     // Application Interrupt and Reset Control Register
16    pub scr: u32,       // System Control Register
17    pub ccr: u32,       // Configuration Control Register
18    pub shp: [u8; 12],  // System Handlers Priority Registers (4-7, 8-11, 12-15)
19    pub shcsr: u32,     // System Handler Control and State Register
20    pub cfsr: u32,      // Configurable Fault Status Register
21    pub hfsr: u32,      // HardFault Status Register
22    pub dfsr: u32,      // Debug Fault Status Register
23    pub mmfar: u32,     // MemManage Fault Address Register
24    pub bfar: u32,      // BusFault Address Register
25    pub afsr: u32,      // Auxiliary Fault Status Register
26    pub pfr: [u32; 2],  // Processor Feature Register
27    pub dfr: u32,       // Debug Feature Register
28    pub adr: u32,       // Auxiliary Feature Register
29    pub mmfr: [u32; 4], // Memory Model Feature Register
30    pub isar: [u32; 5], // Instruction Set Attributes Register
31    _reserved0: [u32; 5],
32    pub cpacr: u32, // Coprocessor Access Control Register
33}
34
35// SCB Peripheral Instance
36pub struct SCB;
37
38impl PeripheralAccess for SCB {
39    const BASE_ADDRESS: u32 = SCB_BASE;
40    type RegisterBlock = Scb;
41}
42
43// SCB CPUID Register Definitions
44pub const SCB_CPUID_IMPLEMENTER_POS: u32 = 24;
45pub const SCB_CPUID_IMPLEMENTER_MSK: u32 = 0xFF << SCB_CPUID_IMPLEMENTER_POS;
46
47pub const SCB_CPUID_VARIANT_POS: u32 = 20;
48pub const SCB_CPUID_VARIANT_MSK: u32 = 0xF << SCB_CPUID_VARIANT_POS;
49
50pub const SCB_CPUID_ARCHITECTURE_POS: u32 = 16;
51pub const SCB_CPUID_ARCHITECTURE_MSK: u32 = 0xF << SCB_CPUID_ARCHITECTURE_POS;
52
53pub const SCB_CPUID_PARTNO_POS: u32 = 4;
54pub const SCB_CPUID_PARTNO_MSK: u32 = 0xFFF << SCB_CPUID_PARTNO_POS;
55
56pub const SCB_CPUID_REVISION_POS: u32 = 0;
57pub const SCB_CPUID_REVISION_MSK: u32 = 0xF;
58
59// SCB Interrupt Control State Register Definitions
60pub const SCB_ICSR_NMIPENDSET_POS: u32 = 31;
61pub const SCB_ICSR_NMIPENDSET_MSK: u32 = 1 << SCB_ICSR_NMIPENDSET_POS;
62
63pub const SCB_ICSR_PENDSVSET_POS: u32 = 28;
64pub const SCB_ICSR_PENDSVSET_MSK: u32 = 1 << SCB_ICSR_PENDSVSET_POS;
65
66pub const SCB_ICSR_PENDSVCLR_POS: u32 = 27;
67pub const SCB_ICSR_PENDSVCLR_MSK: u32 = 1 << SCB_ICSR_PENDSVCLR_POS;
68
69pub const SCB_ICSR_PENDSTSET_POS: u32 = 26;
70pub const SCB_ICSR_PENDSTSET_MSK: u32 = 1 << SCB_ICSR_PENDSTSET_POS;
71
72pub const SCB_ICSR_PENDSTCLR_POS: u32 = 25;
73pub const SCB_ICSR_PENDSTCLR_MSK: u32 = 1 << SCB_ICSR_PENDSTCLR_POS;
74
75pub const SCB_ICSR_ISRPREEMPT_POS: u32 = 23;
76pub const SCB_ICSR_ISRPREEMPT_MSK: u32 = 1 << SCB_ICSR_ISRPREEMPT_POS;
77
78pub const SCB_ICSR_ISRPENDING_POS: u32 = 22;
79pub const SCB_ICSR_ISRPENDING_MSK: u32 = 1 << SCB_ICSR_ISRPENDING_POS;
80
81pub const SCB_ICSR_VECTPENDING_POS: u32 = 12;
82pub const SCB_ICSR_VECTPENDING_MSK: u32 = 0x1FF << SCB_ICSR_VECTPENDING_POS;
83
84pub const SCB_ICSR_RETTOBASE_POS: u32 = 11;
85pub const SCB_ICSR_RETTOBASE_MSK: u32 = 1 << SCB_ICSR_RETTOBASE_POS;
86
87pub const SCB_ICSR_VECTACTIVE_POS: u32 = 0;
88pub const SCB_ICSR_VECTACTIVE_MSK: u32 = 0x1FF;
89
90// SCB Vector Table Offset Register Definitions
91pub const SCB_VTOR_TBLOFF_POS: u32 = 7;
92pub const SCB_VTOR_TBLOFF_MSK: u32 = 0x1FFFFFF << SCB_VTOR_TBLOFF_POS;
93
94// SCB Application Interrupt and Reset Control Register Definitions
95pub const SCB_AIRCR_VECTKEY_POS: u32 = 16;
96pub const SCB_AIRCR_VECTKEY_MSK: u32 = 0xFFFF << SCB_AIRCR_VECTKEY_POS;
97pub const SCB_AIRCR_VECTKEYSTAT_POS: u32 = 16;
98pub const SCB_AIRCR_VECTKEYSTAT_MSK: u32 = 0xFFFF << SCB_AIRCR_VECTKEYSTAT_POS;
99
100pub const SCB_AIRCR_ENDIANESS_POS: u32 = 15;
101pub const SCB_AIRCR_ENDIANESS_MSK: u32 = 1 << SCB_AIRCR_ENDIANESS_POS;
102
103pub const SCB_AIRCR_PRIGROUP_POS: u32 = 8;
104pub const SCB_AIRCR_PRIGROUP_MSK: u32 = 7 << SCB_AIRCR_PRIGROUP_POS;
105
106pub const SCB_AIRCR_SYSRESETREQ_POS: u32 = 2;
107pub const SCB_AIRCR_SYSRESETREQ_MSK: u32 = 1 << SCB_AIRCR_SYSRESETREQ_POS;
108
109pub const SCB_AIRCR_VECTCLRACTIVE_POS: u32 = 1;
110pub const SCB_AIRCR_VECTCLRACTIVE_MSK: u32 = 1 << SCB_AIRCR_VECTCLRACTIVE_POS;
111
112pub const SCB_AIRCR_VECTRESET_POS: u32 = 0;
113pub const SCB_AIRCR_VECTRESET_MSK: u32 = 1;
114
115// SCB System Control Register Definitions
116pub const SCB_SCR_SEVONPEND_POS: u32 = 4;
117pub const SCB_SCR_SEVONPEND_MSK: u32 = 1 << SCB_SCR_SEVONPEND_POS;
118
119pub const SCB_SCR_SLEEPDEEP_POS: u32 = 2;
120pub const SCB_SCR_SLEEPDEEP_MSK: u32 = 1 << SCB_SCR_SLEEPDEEP_POS;
121
122pub const SCB_SCR_SLEEPONEXIT_POS: u32 = 1;
123pub const SCB_SCR_SLEEPONEXIT_MSK: u32 = 1 << SCB_SCR_SLEEPONEXIT_POS;
124
125// SCB Configuration Control Register Definitions
126pub const SCB_CCR_STKALIGN_POS: u32 = 9;
127pub const SCB_CCR_STKALIGN_MSK: u32 = 1 << SCB_CCR_STKALIGN_POS;
128
129pub const SCB_CCR_BFHFNMIGN_POS: u32 = 8;
130pub const SCB_CCR_BFHFNMIGN_MSK: u32 = 1 << SCB_CCR_BFHFNMIGN_POS;
131
132pub const SCB_CCR_DIV_0_TRP_POS: u32 = 4;
133pub const SCB_CCR_DIV_0_TRP_MSK: u32 = 1 << SCB_CCR_DIV_0_TRP_POS;
134
135pub const SCB_CCR_UNALIGN_TRP_POS: u32 = 3;
136pub const SCB_CCR_UNALIGN_TRP_MSK: u32 = 1 << SCB_CCR_UNALIGN_TRP_POS;
137
138pub const SCB_CCR_USERSETMPEND_POS: u32 = 1;
139pub const SCB_CCR_USERSETMPEND_MSK: u32 = 1 << SCB_CCR_USERSETMPEND_POS;
140
141pub const SCB_CCR_NONBASETHRDENA_POS: u32 = 0;
142pub const SCB_CCR_NONBASETHRDENA_MSK: u32 = 1;
143
144// SCB System Handler Control and State Register Definitions
145pub const SCB_SHCSR_USGFAULTENA_POS: u32 = 18;
146pub const SCB_SHCSR_USGFAULTENA_MSK: u32 = 1 << SCB_SHCSR_USGFAULTENA_POS;
147
148pub const SCB_SHCSR_BUSFAULTENA_POS: u32 = 17;
149pub const SCB_SHCSR_BUSFAULTENA_MSK: u32 = 1 << SCB_SHCSR_BUSFAULTENA_POS;
150
151pub const SCB_SHCSR_MEMFAULTENA_POS: u32 = 16;
152pub const SCB_SHCSR_MEMFAULTENA_MSK: u32 = 1 << SCB_SHCSR_MEMFAULTENA_POS;
153
154pub const SCB_SHCSR_SVCALLPENDED_POS: u32 = 15;
155pub const SCB_SHCSR_SVCALLPENDED_MSK: u32 = 1 << SCB_SHCSR_SVCALLPENDED_POS;
156
157pub const SCB_SHCSR_BUSFAULTPENDED_POS: u32 = 14;
158pub const SCB_SHCSR_BUSFAULTPENDED_MSK: u32 = 1 << SCB_SHCSR_BUSFAULTPENDED_POS;
159
160pub const SCB_SHCSR_MEMFAULTPENDED_POS: u32 = 13;
161pub const SCB_SHCSR_MEMFAULTPENDED_MSK: u32 = 1 << SCB_SHCSR_MEMFAULTPENDED_POS;
162
163pub const SCB_SHCSR_USGFAULTPENDED_POS: u32 = 12;
164pub const SCB_SHCSR_USGFAULTPENDED_MSK: u32 = 1 << SCB_SHCSR_USGFAULTPENDED_POS;
165
166pub const SCB_SHCSR_SYSTICKACT_POS: u32 = 11;
167pub const SCB_SHCSR_SYSTICKACT_MSK: u32 = 1 << SCB_SHCSR_SYSTICKACT_POS;
168
169pub const SCB_SHCSR_PENDSVACT_POS: u32 = 10;
170pub const SCB_SHCSR_PENDSVACT_MSK: u32 = 1 << SCB_SHCSR_PENDSVACT_POS;
171
172pub const SCB_SHCSR_MONITORACT_POS: u32 = 8;
173pub const SCB_SHCSR_MONITORACT_MSK: u32 = 1 << SCB_SHCSR_MONITORACT_POS;
174
175pub const SCB_SHCSR_SVCALLACT_POS: u32 = 7;
176pub const SCB_SHCSR_SVCALLACT_MSK: u32 = 1 << SCB_SHCSR_SVCALLACT_POS;
177
178pub const SCB_SHCSR_USGFAULTACT_POS: u32 = 3;
179pub const SCB_SHCSR_USGFAULTACT_MSK: u32 = 1 << SCB_SHCSR_USGFAULTACT_POS;
180
181pub const SCB_SHCSR_BUSFAULTACT_POS: u32 = 1;
182pub const SCB_SHCSR_BUSFAULTACT_MSK: u32 = 1 << SCB_SHCSR_BUSFAULTACT_POS;
183
184pub const SCB_SHCSR_MEMFAULTACT_POS: u32 = 0;
185pub const SCB_SHCSR_MEMFAULTACT_MSK: u32 = 1;
186
187// SCB Configurable Fault Status Register Definitions
188pub const SCB_CFSR_USGFAULTSR_POS: u32 = 16;
189pub const SCB_CFSR_USGFAULTSR_MSK: u32 = 0xFFFF << SCB_CFSR_USGFAULTSR_POS;
190
191pub const SCB_CFSR_BUSFAULTSR_POS: u32 = 8;
192pub const SCB_CFSR_BUSFAULTSR_MSK: u32 = 0xFF << SCB_CFSR_BUSFAULTSR_POS;
193
194pub const SCB_CFSR_MEMFAULTSR_POS: u32 = 0;
195pub const SCB_CFSR_MEMFAULTSR_MSK: u32 = 0xFF;
196
197// MemManage Fault Status Register (part of SCB Configurable Fault Status Register)
198pub const SCB_CFSR_MMARVALID_POS: u32 = SCB_CFSR_MEMFAULTSR_POS + 7;
199pub const SCB_CFSR_MMARVALID_MSK: u32 = 1 << SCB_CFSR_MMARVALID_POS;
200
201pub const SCB_CFSR_MLSPERR_POS: u32 = SCB_CFSR_MEMFAULTSR_POS + 5;
202pub const SCB_CFSR_MLSPERR_MSK: u32 = 1 << SCB_CFSR_MLSPERR_POS;
203
204pub const SCB_CFSR_MSTKERR_POS: u32 = SCB_CFSR_MEMFAULTSR_POS + 4;
205pub const SCB_CFSR_MSTKERR_MSK: u32 = 1 << SCB_CFSR_MSTKERR_POS;
206
207pub const SCB_CFSR_MUNSTKERR_POS: u32 = SCB_CFSR_MEMFAULTSR_POS + 3;
208pub const SCB_CFSR_MUNSTKERR_MSK: u32 = 1 << SCB_CFSR_MUNSTKERR_POS;
209
210pub const SCB_CFSR_DACCVIOL_POS: u32 = SCB_CFSR_MEMFAULTSR_POS + 1;
211pub const SCB_CFSR_DACCVIOL_MSK: u32 = 1 << SCB_CFSR_DACCVIOL_POS;
212
213pub const SCB_CFSR_IACCVIOL_POS: u32 = SCB_CFSR_MEMFAULTSR_POS + 0;
214pub const SCB_CFSR_IACCVIOL_MSK: u32 = 1;
215
216// BusFault Status Register (part of SCB Configurable Fault Status Register)
217pub const SCB_CFSR_BFARVALID_POS: u32 = SCB_CFSR_BUSFAULTSR_POS + 7;
218pub const SCB_CFSR_BFARVALID_MSK: u32 = 1 << SCB_CFSR_BFARVALID_POS;
219
220pub const SCB_CFSR_LSPERR_POS: u32 = SCB_CFSR_BUSFAULTSR_POS + 5;
221pub const SCB_CFSR_LSPERR_MSK: u32 = 1 << SCB_CFSR_LSPERR_POS;
222
223pub const SCB_CFSR_STKERR_POS: u32 = SCB_CFSR_BUSFAULTSR_POS + 4;
224pub const SCB_CFSR_STKERR_MSK: u32 = 1 << SCB_CFSR_STKERR_POS;
225
226pub const SCB_CFSR_UNSTKERR_POS: u32 = SCB_CFSR_BUSFAULTSR_POS + 3;
227pub const SCB_CFSR_UNSTKERR_MSK: u32 = 1 << SCB_CFSR_UNSTKERR_POS;
228
229pub const SCB_CFSR_IMPRECISERR_POS: u32 = SCB_CFSR_BUSFAULTSR_POS + 2;
230pub const SCB_CFSR_IMPRECISERR_MSK: u32 = 1 << SCB_CFSR_IMPRECISERR_POS;
231
232pub const SCB_CFSR_PRECISERR_POS: u32 = SCB_CFSR_BUSFAULTSR_POS + 1;
233pub const SCB_CFSR_PRECISERR_MSK: u32 = 1 << SCB_CFSR_PRECISERR_POS;
234
235pub const SCB_CFSR_IBUSERR_POS: u32 = SCB_CFSR_BUSFAULTSR_POS + 0;
236pub const SCB_CFSR_IBUSERR_MSK: u32 = 1 << SCB_CFSR_IBUSERR_POS;
237
238// UsageFault Status Register (part of SCB Configurable Fault Status Register)
239pub const SCB_CFSR_DIVBYZERO_POS: u32 = SCB_CFSR_USGFAULTSR_POS + 9;
240pub const SCB_CFSR_DIVBYZERO_MSK: u32 = 1 << SCB_CFSR_DIVBYZERO_POS;
241
242pub const SCB_CFSR_UNALIGNED_POS: u32 = SCB_CFSR_USGFAULTSR_POS + 8;
243pub const SCB_CFSR_UNALIGNED_MSK: u32 = 1 << SCB_CFSR_UNALIGNED_POS;
244
245pub const SCB_CFSR_NOCP_POS: u32 = SCB_CFSR_USGFAULTSR_POS + 3;
246pub const SCB_CFSR_NOCP_MSK: u32 = 1 << SCB_CFSR_NOCP_POS;
247
248pub const SCB_CFSR_INVPC_POS: u32 = SCB_CFSR_USGFAULTSR_POS + 2;
249pub const SCB_CFSR_INVPC_MSK: u32 = 1 << SCB_CFSR_INVPC_POS;
250
251pub const SCB_CFSR_INVSTATE_POS: u32 = SCB_CFSR_USGFAULTSR_POS + 1;
252pub const SCB_CFSR_INVSTATE_MSK: u32 = 1 << SCB_CFSR_INVSTATE_POS;
253
254pub const SCB_CFSR_UNDEFINSTR_POS: u32 = SCB_CFSR_USGFAULTSR_POS + 0;
255pub const SCB_CFSR_UNDEFINSTR_MSK: u32 = 1 << SCB_CFSR_UNDEFINSTR_POS;
256
257// SCB Hard Fault Status Register Definitions
258pub const SCB_HFSR_DEBUGEVT_POS: u32 = 31;
259pub const SCB_HFSR_DEBUGEVT_MSK: u32 = 1 << SCB_HFSR_DEBUGEVT_POS;
260
261pub const SCB_HFSR_FORCED_POS: u32 = 30;
262pub const SCB_HFSR_FORCED_MSK: u32 = 1 << SCB_HFSR_FORCED_POS;
263
264pub const SCB_HFSR_VECTTBL_POS: u32 = 1;
265pub const SCB_HFSR_VECTTBL_MSK: u32 = 1 << SCB_HFSR_VECTTBL_POS;
266
267// SCB Debug Fault Status Register Definitions
268pub const SCB_DFSR_EXTERNAL_POS: u32 = 4;
269pub const SCB_DFSR_EXTERNAL_MSK: u32 = 1 << SCB_DFSR_EXTERNAL_POS;
270
271pub const SCB_DFSR_VCATCH_POS: u32 = 3;
272pub const SCB_DFSR_VCATCH_MSK: u32 = 1 << SCB_DFSR_VCATCH_POS;
273
274pub const SCB_DFSR_DWTTRAP_POS: u32 = 2;
275pub const SCB_DFSR_DWTTRAP_MSK: u32 = 1 << SCB_DFSR_DWTTRAP_POS;
276
277pub const SCB_DFSR_BKPT_POS: u32 = 1;
278pub const SCB_DFSR_BKPT_MSK: u32 = 1 << SCB_DFSR_BKPT_POS;
279
280pub const SCB_DFSR_HALTED_POS: u32 = 0;
281pub const SCB_DFSR_HALTED_MSK: u32 = 1;
282
283// SCB Coprocessor Access Control Register Definitions
284pub const SCB_CPACR_CP11_POS: u32 = 22;
285pub const SCB_CPACR_CP11_MSK: u32 = 3 << SCB_CPACR_CP11_POS;
286
287pub const SCB_CPACR_CP10_POS: u32 = 20;
288pub const SCB_CPACR_CP10_MSK: u32 = 3 << SCB_CPACR_CP10_POS;
289
290pub const SCB_CPACR_CP7_POS: u32 = 14;
291pub const SCB_CPACR_CP7_MSK: u32 = 3 << SCB_CPACR_CP7_POS;
292
293pub const SCB_CPACR_CP6_POS: u32 = 12;
294pub const SCB_CPACR_CP6_MSK: u32 = 3 << SCB_CPACR_CP6_POS;
295
296pub const SCB_CPACR_CP5_POS: u32 = 10;
297pub const SCB_CPACR_CP5_MSK: u32 = 3 << SCB_CPACR_CP5_POS;
298
299pub const SCB_CPACR_CP4_POS: u32 = 8;
300pub const SCB_CPACR_CP4_MSK: u32 = 3 << SCB_CPACR_CP4_POS;
301
302pub const SCB_CPACR_CP3_POS: u32 = 6;
303pub const SCB_CPACR_CP3_MSK: u32 = 3 << SCB_CPACR_CP3_POS;
304
305pub const SCB_CPACR_CP2_POS: u32 = 4;
306pub const SCB_CPACR_CP2_MSK: u32 = 3 << SCB_CPACR_CP2_POS;
307
308pub const SCB_CPACR_CP1_POS: u32 = 2;
309pub const SCB_CPACR_CP1_MSK: u32 = 3 << SCB_CPACR_CP1_POS;
310
311pub const SCB_CPACR_CP0_POS: u32 = 0;
312pub const SCB_CPACR_CP0_MSK: u32 = 3 << SCB_CPACR_CP0_POS;
stm32_rust_template/arch/cortex_m4/scb.rs

stm32_rust_template/arch/cortex_m4/
scb.rs
